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<!@TC:1741322765>
#Build: Synplify Pro (R) V-2023.09L-2, Build 349R, Sep 17 2024
#install: C:\Program Files\diamond\3.14\synpbase
#OS: Windows 10 or later
#Hostname: LLAP

# Fri Mar  7 12:46:05 2025

#Implementation: impl1


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\Program Files\diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: LLAP

Implementation : impl1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1741322773> | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\Program Files\diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: LLAP

Implementation : impl1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1741322773> | Running in 64-bit mode 
@I::"C:\Program Files\diamond\3.14\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\Program Files\diamond\3.14\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\Program Files\diamond\3.14\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\bin_to_bcd.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\decoder.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\prox_detect.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\source\SegDecoder.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v" (library work)
@I::"C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\BuzzControl.v" (library work)
Verilog syntax check successful!
File C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\prox_detect.v changed - recompiling
Selecting top level module prox_detect
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:18:7:18:23:@N:CG364:@XP_MSG">rpr0521rs_driver.v(18)</a><!@TM:1741322773> | Synthesizing module rpr0521rs_driver in library work.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:154:56:154:59:@N:CG179:@XP_MSG">rpr0521rs_driver.v(154)</a><!@TM:1741322773> | Removing redundant assignment.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:157:56:157:59:@N:CG179:@XP_MSG">rpr0521rs_driver.v(157)</a><!@TM:1741322773> | Removing redundant assignment.
<font color=#A52A2A>@W:<a href="@W:CG1340:@XP_HELP">CG1340</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:161:47:161:53:@W:CG1340:@XP_MSG">rpr0521rs_driver.v(161)</a><!@TM:1741322773> | Index into variable data_wr could be out of range ; a simulation mismatch is possible.</font>
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:169:53:169:58:@N:CG179:@XP_MSG">rpr0521rs_driver.v(169)</a><!@TM:1741322773> | Removing redundant assignment.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:176:54:176:57:@N:CG179:@XP_MSG">rpr0521rs_driver.v(176)</a><!@TM:1741322773> | Removing redundant assignment.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:179:54:179:57:@N:CG179:@XP_MSG">rpr0521rs_driver.v(179)</a><!@TM:1741322773> | Removing redundant assignment.
Running optimization stage 1 on rpr0521rs_driver .......
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL265:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Removing unused bit 7 of dev_addr[7:0]. Either assign all bits or reduce the width of the signal.</font>
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal dev_addr[6:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal reg_data[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal reg_addr[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal prox_dat[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal data_wr[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal data_r[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal dat_valid. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal dat_l[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal dat_h[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal ch1_dat[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Feedback mux created for signal ch0_dat[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit reg_addr[4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit reg_addr[5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit reg_addr[6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit reg_addr[7] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit reg_data[4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit reg_data[5] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit state_back[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit state_back[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[0] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[2] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Register bit dev_addr[6] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL279:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bits 7 to 4 of reg_addr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL279:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bits 5 to 4 of reg_data[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning unused register ack_cl. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning unused register ack_cl. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL279:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bits 3 to 2 of state_back[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
Finished optimization stage 1 on rpr0521rs_driver (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\bin_to_bcd.v:18:7:18:17:@N:CG364:@XP_MSG">bin_to_bcd.v(18)</a><!@TM:1741322773> | Synthesizing module bin_to_bcd in library work.
<font color=#A52A2A>@W:<a href="@W:CG215:@XP_HELP">CG215</a> : <a href="C:\Program Files\diamond\3.14\synpbase\lib\lucent\machxo2.v:@W:CG215:@XP_MSG">machxo2.v</a><!@TM:1741322773> | Unrecognized attribute .repeat_statement on loop statement</font>
Running optimization stage 1 on bin_to_bcd .......
Finished optimization stage 1 on bin_to_bcd (CPU Time 0h:00m:01s, Memory Used current: 139MB peak: 139MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\decoder.v:18:7:18:14:@N:CG364:@XP_MSG">decoder.v(18)</a><!@TM:1741322773> | Synthesizing module decoder in library work.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\decoder.v:34:15:34:24:@N:CG179:@XP_MSG">decoder.v(34)</a><!@TM:1741322773> | Removing redundant assignment.
Running optimization stage 1 on decoder .......
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\decoder.v:30:0:30:6:@W:CL279:@XP_MSG">decoder.v(30)</a><!@TM:1741322773> | Pruning register bits 15 to 12 of prox_dat2[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\decoder.v:30:0:30:6:@W:CL279:@XP_MSG">decoder.v(30)</a><!@TM:1741322773> | Pruning register bits 8 to 0 of prox_dat2[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
Finished optimization stage 1 on decoder (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 140MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:18:7:18:19:@N:CG364:@XP_MSG">segment_scan.v(18)</a><!@TM:1741322773> | Synthesizing module segment_scan in library work.
Running optimization stage 1 on segment_scan .......
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:87:0:87:6:@A:CL282:@XP_MSG">segment_scan.v(87)</a><!@TM:1741322773> | Feedback mux created for signal data[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[0][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[1][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[2][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[3][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[4][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[5][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[6][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[7][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[8][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[9][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[10][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[11][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[12][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[13][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[14][6:0]. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:47:0:47:6:@W:CL169:@XP_MSG">segment_scan.v(47)</a><!@TM:1741322773> | Pruning unused register seg[15][6:0]. Make sure that there are no unused intermediate registers.</font>
Finished optimization stage 1 on segment_scan (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\source\SegDecoder.v:1:7:1:20:@N:CG364:@XP_MSG">SegDecoder.v(1)</a><!@TM:1741322773> | Synthesizing module HexSegDecoder in library work.
Running optimization stage 1 on HexSegDecoder .......
Finished optimization stage 1 on HexSegDecoder (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v:39:7:39:12:@N:CG364:@XP_MSG">Timer.v(39)</a><!@TM:1741322773> | Synthesizing module timer in library work.

	WIDTH=32'b00000000000000000000000000100100
	N=32'b00000000000000000001001110001000
   Generated name = timer_36s_5000s
Running optimization stage 1 on timer_36s_5000s .......
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v:83:1:83:7:@W:CL169:@XP_MSG">Timer.v(83)</a><!@TM:1741322773> | Pruning unused register clk_n. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v:73:1:73:7:@W:CL169:@XP_MSG">Timer.v(73)</a><!@TM:1741322773> | Pruning unused register cnt_n[35:0]. Make sure that there are no unused intermediate registers.</font>
Finished optimization stage 1 on timer_36s_5000s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v:39:7:39:12:@N:CG364:@XP_MSG">Timer.v(39)</a><!@TM:1741322773> | Synthesizing module timer in library work.

	WIDTH=32'b00000000000000000000000000100100
	N=32'b00000000101101110001101100000000
   Generated name = timer_36s_12000000s
Running optimization stage 1 on timer_36s_12000000s .......
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v:83:1:83:7:@W:CL169:@XP_MSG">Timer.v(83)</a><!@TM:1741322773> | Pruning unused register clk_n. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\Timer.v:73:1:73:7:@W:CL169:@XP_MSG">Timer.v(73)</a><!@TM:1741322773> | Pruning unused register cnt_n[35:0]. Make sure that there are no unused intermediate registers.</font>
Finished optimization stage 1 on timer_36s_12000000s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\BuzzControl.v:1:7:1:18:@N:CG364:@XP_MSG">BuzzControl.v(1)</a><!@TM:1741322773> | Synthesizing module BuzzControl in library work.

	width=32'b00000000000000000000000000100100
	buzzDiv1=32'b00000000000000000001001110001000
	buzzDiv2=32'b00000000101101110001101100000000
   Generated name = BuzzControl_36s_5000s_12000000s
Running optimization stage 1 on BuzzControl_36s_5000s_12000000s .......
Finished optimization stage 1 on BuzzControl_36s_5000s_12000000s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\prox_detect.v:1:7:1:18:@N:CG364:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322773> | Synthesizing module prox_detect in library work.
<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\prox_detect.v:13:13:13:19:@W:CG360:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322773> | Removing wire digit2, as there is no assignment to it.</font>
Running optimization stage 1 on prox_detect .......
<font color=#A52A2A>@W:<a href="@W:CL318:@XP_HELP">CL318</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\prox_detect.v:13:13:13:19:@W:CL318:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322773> | *Output digit2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.</font>
Finished optimization stage 1 on prox_detect (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on prox_detect .......
Finished optimization stage 2 on prox_detect (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on BuzzControl_36s_5000s_12000000s .......
Finished optimization stage 2 on BuzzControl_36s_5000s_12000000s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on timer_36s_12000000s .......
Finished optimization stage 2 on timer_36s_12000000s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on timer_36s_5000s .......
Finished optimization stage 2 on timer_36s_5000s (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on HexSegDecoder .......
Finished optimization stage 2 on HexSegDecoder (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on segment_scan .......
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:68:0:68:6:@W:CL190:@XP_MSG">segment_scan.v(68)</a><!@TM:1741322773> | Optimizing register bit cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:68:0:68:6:@W:CL260:@XP_MSG">segment_scan.v(68)</a><!@TM:1741322773> | Pruning register bit 9 of cnt[9:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\segment_scan.v:87:0:87:6:@N:CL201:@XP_MSG">segment_scan.v(87)</a><!@TM:1741322773> | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   000
   001
   010
Finished optimization stage 2 on segment_scan (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 149MB)
Running optimization stage 2 on decoder .......
Finished optimization stage 2 on decoder (CPU Time 0h:00m:00s, Memory Used current: 114MB peak: 149MB)
Running optimization stage 2 on bin_to_bcd .......
<font color=#A52A2A>@W:<a href="@W:CL247:@XP_HELP">CL247</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\bin_to_bcd.v:21:16:21:24:@W:CL247:@XP_MSG">bin_to_bcd.v(21)</a><!@TM:1741322773> | Input port bit 0 of bin_code[31:0] is unused</font>

Finished optimization stage 2 on bin_to_bcd (CPU Time 0h:00m:02s, Memory Used current: 130MB peak: 149MB)
Running optimization stage 2 on rpr0521rs_driver .......
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit cnt_mode1[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit cnt_start[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit cnt_stop[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit cnt_read[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit cnt_write[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Optimizing register bit cnt[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 3 of cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 3 of cnt_write[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 3 of cnt_read[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 3 of cnt_stop[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 3 of cnt_start[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 3 of cnt_mode1[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@N:CL201:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 12 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 5 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322773> | Pruning register bit 7 of reg_data[7:6]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
Finished optimization stage 2 on rpr0521rs_driver (CPU Time 0h:00m:00s, Memory Used current: 124MB peak: 149MB)

For a summary of runtime per design unit, please see file:
==========================================================
Linked File:  <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\layer0.duruntime:@XP_FILE">layer0.duruntime</a>



At c_ver Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 124MB peak: 149MB)

Process took 0h:00m:08s realtime, 0h:00m:08s cputime

Process completed successfully.
# Fri Mar  7 12:46:13 2025

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\Program Files\diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: LLAP

Implementation : impl1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1741322773> | Running in 64-bit mode 
File C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Mar  7 12:46:13 2025

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_comp.rt.csv:@XP_FILE">prox_detect_impl1_comp.rt.csv</a>

@END

At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 24MB peak: 24MB)

Process took 0h:00m:08s realtime, 0h:00m:08s cputime

Process completed successfully.
# Fri Mar  7 12:46:13 2025

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1741322765>
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\Program Files\diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: LLAP

Implementation : impl1
<a name=compilerReport9></a>Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 349R, Built Sep 17 2024 08:16:26, @</a>

@N: : <!@TM:1741322775> | Running in 64-bit mode 
File C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Fri Mar  7 12:46:15 2025

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1741322765>
# Fri Mar  7 12:46:15 2025


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\Program Files\diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: LLAP

Implementation : impl1
<a name=mapperReport15></a>Synopsys Lattice Technology Pre-mapping, Version map202309lat, Build 191R, Built Sep 17 2024 10:38:50, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 199MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1741322779> | No constraint file specified. 
Linked File:  <a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1_scck.rpt:@XP_FILE">prox_detect_impl1_scck.rpt</a>
See clock summary report "C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1_scck.rpt"
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1741322779> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1741322779> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1741322779> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 194MB peak: 199MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 194MB peak: 199MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 206MB peak: 206MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 207MB peak: 208MB)

NConnInternalConnection caching is on
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1741322779> | Applying initial value "0" on instance clk_40khz. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1741322779> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 257MB peak: 257MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 257MB peak: 257MB)

@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_1 (in view: work.prox_detect(verilog)) on net digit2[8] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_2 (in view: work.prox_detect(verilog)) on net digit2[7] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_3 (in view: work.prox_detect(verilog)) on net digit2[6] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_4 (in view: work.prox_detect(verilog)) on net digit2[5] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_5 (in view: work.prox_detect(verilog)) on net digit2[4] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_6 (in view: work.prox_detect(verilog)) on net digit2[3] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_7 (in view: work.prox_detect(verilog)) on net digit2[2] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_8 (in view: work.prox_detect(verilog)) on net digit2[1] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322779> | Tristate driver digit2_9 (in view: work.prox_detect(verilog)) on net digit2[0] (in view: work.prox_detect(verilog)) has its enable tied to GND.

Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 257MB peak: 257MB)


Finished DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 257MB peak: 258MB)

Encoding state machine state[11:0] (in view: work.rpr0521rs_driver(verilog))
original code -> new code
   0000 -> 000000000001
   0001 -> 000000000010
   0010 -> 000000000100
   0011 -> 000000001000
   0100 -> 000000010000
   0101 -> 000000100000
   0110 -> 000001000000
   0111 -> 000010000000
   1000 -> 000100000000
   1001 -> 001000000000
   1010 -> 010000000000
   1011 -> 100000000000
Encoding state machine state[2:0] (in view: work.segment_scan(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 261MB peak: 261MB)


mixed edge conversion for GCC is OFF
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1741322779> | Incompatible asynchronous control logic preventing generated clock conversion. 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1741322779> | GCC encountered Inferred Clock constraint on net GCC considers to be data u3.clk_40khz; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1741322779> | GCC encountered Inferred Clock constraint on net GCC considers to be data u1.clk_400khz; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1741322779> | GCC encountered Inferred Clock constraint on net GCC considers to be data u1.dat_valid; this will likely lead to failure to convert</font> 

Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 261MB peak: 262MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 262MB peak: 262MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 262MB peak: 262MB)

@N:<a href="@N:FX1184:@XP_HELP">FX1184</a> : <!@TM:1741322779> | Applying syn_allowed_resources blockrams=10 on top level netlist prox_detect  

Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 262MB peak: 262MB)



<a name=mapperReport16></a>Clock Summary</a>
******************

          Start                                            Requested     Requested     Clock                                                        Clock          Clock
Level     Clock                                            Frequency     Period        Type                                                         Group          Load 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       prox_detect|clk                                  200.0 MHz     5.000         inferred                                                     (multiple)     98   
1 .         rpr0521rs_driver|clk_400khz_derived_clock      200.0 MHz     5.000         derived (from prox_detect|clk)                               (multiple)     183  
2 ..          rpr0521rs_driver|dat_valid_derived_clock     200.0 MHz     5.000         derived (from rpr0521rs_driver|clk_400khz_derived_clock)     (multiple)     35   
1 .         segment_scan|clk_40khz_derived_clock           200.0 MHz     5.000         derived (from prox_detect|clk)                               (multiple)     30   
========================================================================================================================================================================



Clock Load Summary
***********************

                                              Clock     Source                        Clock Pin                Non-clock Pin     Non-clock Pin
Clock                                         Load      Pin                           Seq Example              Seq Example       Comb Example 
----------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                               98        clk(port)                     buzz_ctrl.C              -                 -            
rpr0521rs_driver|clk_400khz_derived_clock     183       u1.clk_400khz.Q[0](dffre)     u1.num_delay[23:0].C     -                 -            
rpr0521rs_driver|dat_valid_derived_clock      35        u1.dat_valid.Q[0](dffe)       u2.prox_dat0[15:0].C     -                 -            
segment_scan|clk_40khz_derived_clock          30        u3.clk_40khz.Q[0](dffr)       u3.seg_sck.C             -                 -            
==============================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:49:1:49:7:@W:MT529:@XP_MSG">rpr0521rs_driver.v(49)</a><!@TM:1741322779> | Found inferred clock prox_detect|clk which controls 98 sequential elements including u1.cnt_400khz[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport17></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 98 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 248 clock pin(s) of sequential element(s)
0 instances converted, 248 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_prem.srm@|S:clk@|E:led_reg@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       clk                 port                   98         led_reg        
=======================================================================================
================================================================ Gated/Generated Clocks ================================================================
Clock Tree ID     Driving Element        Drive Element Type     Unconverted Fanout     Sample Instance        Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_prem.srm@|S:u3.clk_40khz.Q[0]@|E:u3.state[1]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       u3.clk_40khz.Q[0]      dffr                   30                     u3.state[1]            Derived clock on input (not legal for GCC)
<a href="@|L:C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_prem.srm@|S:u1.dat_valid.Q[0]@|E:u2.prox_dat2[11:9]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       u1.dat_valid.Q[0]      dffe                   35                     u2.prox_dat2[11:9]     Derived clock on input (not legal for GCC)
<a href="@|L:C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_prem.srm@|S:u1.clk_400khz.Q[0]@|E:u1.state[11]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       u1.clk_400khz.Q[0]     dffre                  183                    u1.state[11]           Derived clock on input (not legal for GCC)
========================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######


Summary of user generated gated clocks:
0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

@N:<a href="@N:FX1143:@XP_HELP">FX1143</a> : <!@TM:1741322779> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:01s; Memory used current: 262MB peak: 262MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:01s; Memory used current: 263MB peak: 263MB)


Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:01s; Memory used current: 263MB peak: 263MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 178MB peak: 264MB)

Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Fri Mar  7 12:46:18 2025

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1741322765>
# Fri Mar  7 12:46:19 2025


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\Program Files\diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: LLAP

Implementation : impl1
<a name=mapperReport23></a>Synopsys Lattice Technology Mapper, Version map202309lat, Build 191R, Built Sep 17 2024 10:38:50, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1741322986> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1741322986> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1741322986> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 199MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 199MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 200MB peak: 200MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 201MB peak: 203MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 256MB peak: 256MB)

@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_1 (in view: work.prox_detect(verilog)) on net digit2[8] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_2 (in view: work.prox_detect(verilog)) on net digit2[7] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_3 (in view: work.prox_detect(verilog)) on net digit2[6] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_4 (in view: work.prox_detect(verilog)) on net digit2[5] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_5 (in view: work.prox_detect(verilog)) on net digit2[4] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_6 (in view: work.prox_detect(verilog)) on net digit2[3] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_7 (in view: work.prox_detect(verilog)) on net digit2[2] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_8 (in view: work.prox_detect(verilog)) on net digit2[1] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_9 (in view: work.prox_detect(verilog)) on net digit2[0] (in view: work.prox_detect(verilog)) has its enable tied to GND.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:89:6:89:10:@N:BZ173:@XP_MSG">rpr0521rs_driver.v(89)</a><!@TM:1741322986> | ROM state_2[3:1] (in view: work.rpr0521rs_driver(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:89:6:89:10:@N:BZ173:@XP_MSG">rpr0521rs_driver.v(89)</a><!@TM:1741322986> | ROM state_2[3:1] (in view: work.rpr0521rs_driver(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:89:6:89:10:@N:MO106:@XP_MSG">rpr0521rs_driver.v(89)</a><!@TM:1741322986> | Found ROM state_2[3:1] (in view: work.rpr0521rs_driver(verilog)) with 12 words by 3 bits.
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:18:7:18:23:@W:BN161:@XP_MSG">rpr0521rs_driver.v(18)</a><!@TM:1741322986> | Net i2c_sda has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:18:7:18:23:@W:BN161:@XP_MSG">rpr0521rs_driver.v(18)</a><!@TM:1741322986> | Net sda_2 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:18:7:18:23:@W:BN161:@XP_MSG">rpr0521rs_driver.v(18)</a><!@TM:1741322986> | Net sda_cl_4 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:18:7:18:23:@W:BN161:@XP_MSG">rpr0521rs_driver.v(18)</a><!@TM:1741322986> | Net sda_4_1 has multiple drivers .</font>
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:112:32:112:43:@N:BZ173:@XP_MSG">segment_scan.v(112)</a><!@TM:1741322986> | ROM data_9[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:111:32:111:43:@N:BZ173:@XP_MSG">segment_scan.v(111)</a><!@TM:1741322986> | ROM data_8[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:110:32:110:43:@N:BZ173:@XP_MSG">segment_scan.v(110)</a><!@TM:1741322986> | ROM data_7[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:109:32:109:43:@N:BZ173:@XP_MSG">segment_scan.v(109)</a><!@TM:1741322986> | ROM data_6[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:108:32:108:43:@N:BZ173:@XP_MSG">segment_scan.v(108)</a><!@TM:1741322986> | ROM data_5[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:107:32:107:43:@N:BZ173:@XP_MSG">segment_scan.v(107)</a><!@TM:1741322986> | ROM data_4[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:106:32:106:43:@N:BZ173:@XP_MSG">segment_scan.v(106)</a><!@TM:1741322986> | ROM data_3[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:105:32:105:43:@N:BZ173:@XP_MSG">segment_scan.v(105)</a><!@TM:1741322986> | ROM data_2[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:112:32:112:43:@N:BZ173:@XP_MSG">segment_scan.v(112)</a><!@TM:1741322986> | ROM data_9[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:112:32:112:43:@N:MO106:@XP_MSG">segment_scan.v(112)</a><!@TM:1741322986> | Found ROM data_9[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:111:32:111:43:@N:BZ173:@XP_MSG">segment_scan.v(111)</a><!@TM:1741322986> | ROM data_8[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:111:32:111:43:@N:MO106:@XP_MSG">segment_scan.v(111)</a><!@TM:1741322986> | Found ROM data_8[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:110:32:110:43:@N:BZ173:@XP_MSG">segment_scan.v(110)</a><!@TM:1741322986> | ROM data_7[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:110:32:110:43:@N:MO106:@XP_MSG">segment_scan.v(110)</a><!@TM:1741322986> | Found ROM data_7[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:109:32:109:43:@N:BZ173:@XP_MSG">segment_scan.v(109)</a><!@TM:1741322986> | ROM data_6[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:109:32:109:43:@N:MO106:@XP_MSG">segment_scan.v(109)</a><!@TM:1741322986> | Found ROM data_6[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:108:32:108:43:@N:BZ173:@XP_MSG">segment_scan.v(108)</a><!@TM:1741322986> | ROM data_5[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:108:32:108:43:@N:MO106:@XP_MSG">segment_scan.v(108)</a><!@TM:1741322986> | Found ROM data_5[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:107:32:107:43:@N:BZ173:@XP_MSG">segment_scan.v(107)</a><!@TM:1741322986> | ROM data_4[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:107:32:107:43:@N:MO106:@XP_MSG">segment_scan.v(107)</a><!@TM:1741322986> | Found ROM data_4[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:106:32:106:43:@N:BZ173:@XP_MSG">segment_scan.v(106)</a><!@TM:1741322986> | ROM data_3[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:106:32:106:43:@N:MO106:@XP_MSG">segment_scan.v(106)</a><!@TM:1741322986> | Found ROM data_3[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:105:32:105:43:@N:BZ173:@XP_MSG">segment_scan.v(105)</a><!@TM:1741322986> | ROM data_2[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:105:32:105:43:@N:MO106:@XP_MSG">segment_scan.v(105)</a><!@TM:1741322986> | Found ROM data_2[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\impl1\source\segdecoder.v:14:2:14:6:@N:BZ173:@XP_MSG">segdecoder.v(14)</a><!@TM:1741322986> | ROM u4.seg_1[6:0] (in view: work.prox_detect(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\impl1\source\segdecoder.v:14:2:14:6:@N:BZ173:@XP_MSG">segdecoder.v(14)</a><!@TM:1741322986> | ROM u4.seg_1[6:0] (in view: work.prox_detect(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\impl1\source\segdecoder.v:14:2:14:6:@N:MO106:@XP_MSG">segdecoder.v(14)</a><!@TM:1741322986> | Found ROM u4.seg_1[6:0] (in view: work.prox_detect(verilog)) with 8 words by 7 bits.
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net i2c_sda has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[0] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[1] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[2] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[3] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[4] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[5] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[6] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[7] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit2[8] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net digit1[6] has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net N_12 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net N_15 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net N_25 has multiple drivers .</font>

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 267MB peak: 267MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[23] because it is equivalent to instance u1.num_delay[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[22] because it is equivalent to instance u1.num_delay[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[21] because it is equivalent to instance u1.num_delay[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[20] because it is equivalent to instance u1.num_delay[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[19] because it is equivalent to instance u1.num_delay[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[18] because it is equivalent to instance u1.num_delay[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[17] because it is equivalent to instance u1.num_delay[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[16] because it is equivalent to instance u1.num_delay[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[15] because it is equivalent to instance u1.num_delay[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[14] because it is equivalent to instance u1.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[13] because it is equivalent to instance u1.num_delay[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[11] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[8] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[5] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[4] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[3] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[2] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[1] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[10] because it is equivalent to instance u1.num_delay[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.reg_data[6] because it is equivalent to instance u1.reg_data[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[9] because it is equivalent to instance u1.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[7] because it is equivalent to instance u1.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.num_delay[6] because it is equivalent to instance u1.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MO231:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Found counter in view:work.rpr0521rs_driver(verilog) instance cnt_delay[23:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MO231:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Found counter in view:work.rpr0521rs_driver(verilog) instance cnt_mode2[3:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MO231:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Found counter in view:work.rpr0521rs_driver(verilog) instance cnt_main[3:0] 
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:BN362:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing sequential instance state[9] (in view: work.rpr0521rs_driver(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:BN362:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing sequential instance num_delay[0] (in view: work.rpr0521rs_driver(verilog)) because it does not drive other instances.
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:87:0:87:6:@N:MO231:@XP_MSG">segment_scan.v(87)</a><!@TM:1741322986> | Found counter in view:work.segment_scan(verilog) instance cnt_write[5:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\segment_scan.v:68:0:68:6:@N:MO231:@XP_MSG">segment_scan.v(68)</a><!@TM:1741322986> | Found counter in view:work.segment_scan(verilog) instance cnt[8:0] 
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1741322986> | Applying initial value "0" on instance clk_40khz. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1741322986> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 271MB peak: 271MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing instance u1.state[11] because it is equivalent to instance u1.state[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:BN362:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing sequential instance u1.state[10] (in view: work.prox_detect(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 303MB peak: 303MB)


Available hyper_sources - for debug and ip models
	None Found

NConnInternalConnection caching is on
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net dat_valid has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.clk_40khz has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_102 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_572 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_573 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_574 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_575 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_576 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_577 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_578 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_579 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_580 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_581 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_582 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_583 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_584 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_585 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_586 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_587 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_588 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_589 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u3.N_590 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.clk_400khz has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_110 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_113 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_116 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.un1_cnt_delay_6 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.un1_cnt_delay_7 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.un1_cnt_delay_9 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.un1_cnt_delay_12 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_273 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_274 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_275 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_276 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_277 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_278 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_279 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_280 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_282 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_283 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_284 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_285 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_286 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_287 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_288 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_289 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_290 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_291 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_292 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_293 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_294 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_295 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_296 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_297 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_298 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_299 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_300 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_301 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_302 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_303 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_304 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_305 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_306 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_307 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_308 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_309 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_310 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_311 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_312 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_313 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_314 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_315 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_316 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_317 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_318 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_319 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_320 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_321 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_322 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_323 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_324 has multiple drivers .</font>
<font color=#A52A2A>@W:<a href="@W:BN161:@XP_HELP">BN161</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:1:7:1:18:@W:BN161:@XP_MSG">prox_detect.v(1)</a><!@TM:1741322986> | Net u1.N_325 has multiple drivers .</font>

Only the first 100 messages of id 'BN161' are reported. To see all messages use 'report_messages -log C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synlog\prox_detect_impl1_fpga_mapper.srr -id BN161' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN161} -count unlimited' in the Tcl shell.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 285MB peak: 304MB)

@N:<a href="@N:FA113:@XP_HELP">FA113</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\decoder.v:61:1:61:3:@N:FA113:@XP_MSG">decoder.v(61)</a><!@TM:1741322986> | Pipelining module un1_lux_1[28:0]. For more information, search for "pipelining" in Online Help.
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Pushed in register ch0_dat[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Pushed in register dat_l[7:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Pushed in register dat_h[7:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Pushed in register ch1_dat[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Pushed in register prox_dat[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Pushed in register data_r[7:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\decoder.v:30:0:30:6:@N:MF169:@XP_MSG">decoder.v(30)</a><!@TM:1741322986> | Pushed in register prox_dat0[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\decoder.v:30:0:30:6:@N:MF169:@XP_MSG">decoder.v(30)</a><!@TM:1741322986> | Pushed in register prox_dat1[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\decoder.v:30:0:30:6:@N:MF169:@XP_MSG">decoder.v(30)</a><!@TM:1741322986> | Pushed in register prox_dat2[11:9].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:88:0:88:6:@N:MF169:@XP_MSG">prox_detect.v(88)</a><!@TM:1741322986> | Pushed in register buzz_ctrl.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 293MB peak: 304MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:24s; Memory used current: 352MB peak: 352MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 352MB peak: 352MB)


Finished preparing to map (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 352MB peak: 353MB)


Finished technology mapping (Real Time elapsed 0h:03m:07s; CPU Time elapsed 0h:03m:07s; Memory used current: 378MB peak: 593MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:03m:07s		   -69.91ns		1452 /       606
   2		0h:03m:07s		   -69.31ns		1438 /       606
   3		0h:03m:07s		   -66.44ns		1438 /       606
   4		0h:03m:07s		   -67.84ns		1438 /       606
   5		0h:03m:07s		   -67.43ns		1438 /       606
   6		0h:03m:07s		   -67.68ns		1438 /       606
   7		0h:03m:07s		   -67.92ns		1439 /       606
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[0] (in view: work.prox_detect(verilog)) with 38 loads 3 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[1] (in view: work.prox_detect(verilog)) with 26 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[2] (in view: work.prox_detect(verilog)) with 25 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[3] (in view: work.prox_detect(verilog)) with 17 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[4] (in view: work.prox_detect(verilog)) with 17 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[6] (in view: work.prox_detect(verilog)) with 16 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch1_dat[0] (in view: work.prox_detect(verilog)) with 18 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch1_dat[5] (in view: work.prox_detect(verilog)) with 17 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[5] (in view: work.prox_detect(verilog)) with 16 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[7] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch0_dat[8] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch1_dat[6] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch1_dat[4] (in view: work.prox_detect(verilog)) with 16 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Replicating instance u1.ch1_dat[3] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
Timing driven replication report
Added 29 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   8		0h:03m:09s		   -67.58ns		1440 /       635
   9		0h:03m:09s		   -68.59ns		1445 /       635
  10		0h:03m:09s		   -68.35ns		1446 /       635
  11		0h:03m:10s		   -65.14ns		1454 /       635
  12		0h:03m:10s		   -64.42ns		1458 /       635
  13		0h:03m:10s		   -63.38ns		1461 /       635
  14		0h:03m:10s		   -63.10ns		1462 /       635
  15		0h:03m:10s		   -61.95ns		1469 /       635
  16		0h:03m:11s		   -61.95ns		1469 /       635
  17		0h:03m:11s		   -60.31ns		1472 /       635
  18		0h:03m:11s		   -60.09ns		1472 /       635
  19		0h:03m:11s		   -59.16ns		1480 /       635
  20		0h:03m:11s		   -59.29ns		1479 /       635
  21		0h:03m:12s		   -58.41ns		1483 /       635
  22		0h:03m:12s		   -58.17ns		1483 /       635
  23		0h:03m:12s		   -57.94ns		1486 /       635
  24		0h:03m:12s		   -57.60ns		1494 /       635
  25		0h:03m:12s		   -57.30ns		1495 /       635
  26		0h:03m:12s		   -57.14ns		1495 /       635
  27		0h:03m:13s		   -56.82ns		1498 /       635
  28		0h:03m:13s		   -56.72ns		1498 /       635
  29		0h:03m:13s		   -56.38ns		1503 /       635
  30		0h:03m:13s		   -56.65ns		1503 /       635
  31		0h:03m:14s		   -55.94ns		1506 /       635
  32		0h:03m:14s		   -55.92ns		1506 /       635
  33		0h:03m:14s		   -55.55ns		1507 /       635
  34		0h:03m:14s		   -55.46ns		1509 /       635
  35		0h:03m:14s		   -55.18ns		1513 /       635
  36		0h:03m:15s		   -54.78ns		1510 /       635
  37		0h:03m:15s		   -54.78ns		1510 /       635
  38		0h:03m:15s		   -54.72ns		1516 /       635
  39		0h:03m:16s		   -54.49ns		1518 /       635
  40		0h:03m:16s		   -54.38ns		1527 /       635
  41		0h:03m:16s		   -54.51ns		1528 /       635
  42		0h:03m:17s		   -54.11ns		1533 /       635
  43		0h:03m:17s		   -54.17ns		1535 /       635
  44		0h:03m:18s		   -53.95ns		1534 /       635


  45		0h:03m:18s		   -52.60ns		1562 /       635
  46		0h:03m:19s		   -51.48ns		1573 /       635
  47		0h:03m:19s		   -51.22ns		1580 /       635
  48		0h:03m:19s		   -51.71ns		1581 /       635
  49		0h:03m:20s		   -51.71ns		1582 /       635
  50		0h:03m:20s		   -51.22ns		1583 /       635
  51		0h:03m:20s		   -51.06ns		1588 /       635
  52		0h:03m:20s		   -50.88ns		1589 /       635
  53		0h:03m:21s		   -50.92ns		1593 /       635
  54		0h:03m:22s		   -50.91ns		1600 /       635
  55		0h:03m:22s		   -50.87ns		1602 /       635
  56		0h:03m:22s		   -51.27ns		1603 /       635
  57		0h:03m:22s		   -51.27ns		1602 /       635
  58		0h:03m:22s		   -51.07ns		1603 /       635

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:03m:23s; CPU Time elapsed 0h:03m:23s; Memory used current: 381MB peak: 593MB)

@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\rpr0521rs_driver.v:70:1:70:7:@N:BN362:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741322986> | Removing sequential instance u1.num_delay[12] (in view: work.prox_detect(verilog)) because it does not drive other instances.
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1741322986> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
@N:<a href="@N:MO111:@XP_HELP">MO111</a> : <a href="c:\users\lumfl\downloads\netdisk\v4.0\step-mxo2\mytrafficlight\source\prox_detect.v:13:13:13:19:@N:MO111:@XP_MSG">prox_detect.v(13)</a><!@TM:1741322986> | Tristate driver digit2_obuft_0_.un1[0] (in view: work.prox_detect(verilog)) on net digit2[0] (in view: work.prox_detect(verilog)) has its enable tied to GND.

Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
   buzz_ctrl (in view: work.prox_detect(verilog))
   led_reg (in view: work.prox_detect(verilog))
   u1.ch0_dat[15] (in view: work.prox_detect(verilog))
   u1.ch0_dat[14] (in view: work.prox_detect(verilog))
   u1.ch0_dat[13] (in view: work.prox_detect(verilog))
   u1.ch0_dat[12] (in view: work.prox_detect(verilog))
   u1.ch0_dat[11] (in view: work.prox_detect(verilog))
   u1.ch0_dat[10] (in view: work.prox_detect(verilog))
   u1.ch0_dat[9] (in view: work.prox_detect(verilog))
   u1.ch0_dat[8] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[8] (in view: work.prox_detect(verilog))
   u1.ch0_dat[7] (in view: work.prox_detect(verilog))
   u1.ch0_dat[6] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[6] (in view: work.prox_detect(verilog))
   u1.ch0_dat[5] (in view: work.prox_detect(verilog))
   u1.ch0_dat[4] (in view: work.prox_detect(verilog))
   u1.ch0_dat[3] (in view: work.prox_detect(verilog))
   u1.ch0_dat[2] (in view: work.prox_detect(verilog))
   u1.ch0_dat[1] (in view: work.prox_detect(verilog))
   u1.ch0_dat[0] (in view: work.prox_detect(verilog))
   u1.ch0_dat_0_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_0_rep2 (in view: work.prox_detect(verilog))
   u1.ch0_dat_1_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_2_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_3_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_4_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_5_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_6_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_7_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_8_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[7] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[5] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[4] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[3] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[2] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[1] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[0] (in view: work.prox_detect(verilog))
   u1.ch1_dat[15] (in view: work.prox_detect(verilog))
   u1.ch1_dat[14] (in view: work.prox_detect(verilog))
   u1.ch1_dat[13] (in view: work.prox_detect(verilog))
   u1.ch1_dat[12] (in view: work.prox_detect(verilog))
   u1.ch1_dat[11] (in view: work.prox_detect(verilog))
   u1.ch1_dat[10] (in view: work.prox_detect(verilog))
   u1.ch1_dat[9] (in view: work.prox_detect(verilog))
   u1.ch1_dat[8] (in view: work.prox_detect(verilog))
   u1.ch1_dat[7] (in view: work.prox_detect(verilog))
   u1.ch1_dat_3_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[6] (in view: work.prox_detect(verilog))
   u1.ch1_dat[6] (in view: work.prox_detect(verilog))
   u1.ch1_dat[5] (in view: work.prox_detect(verilog))
   u1.ch1_dat[2] (in view: work.prox_detect(verilog))
   u1.ch1_dat_0_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_4_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[5] (in view: work.prox_detect(verilog))
   u1.ch1_dat[4] (in view: work.prox_detect(verilog))
   u1.ch1_dat[1] (in view: work.prox_detect(verilog))
   u1.ch1_dat_5_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[4] (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[3] (in view: work.prox_detect(verilog))
   u1.ch1_dat[3] (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[0] (in view: work.prox_detect(verilog))
   u1.ch1_dat[0] (in view: work.prox_detect(verilog))
   u1.ch1_dat_6_rep1 (in view: work.prox_detect(verilog))
   u1.dat_h[7] (in view: work.prox_detect(verilog))
   u1.dat_h[6] (in view: work.prox_detect(verilog))
   u1.dat_h[5] (in view: work.prox_detect(verilog))
   u1.dat_h[4] (in view: work.prox_detect(verilog))
   u1.dat_h[3] (in view: work.prox_detect(verilog))
   u1.dat_h[2] (in view: work.prox_detect(verilog))
   u1.dat_h[1] (in view: work.prox_detect(verilog))
   u1.dat_h[0] (in view: work.prox_detect(verilog))
   u1.dat_l[7] (in view: work.prox_detect(verilog))
   u1.dat_l[6] (in view: work.prox_detect(verilog))
   u1.dat_l[5] (in view: work.prox_detect(verilog))
   u1.dat_l[4] (in view: work.prox_detect(verilog))
   u1.dat_l[3] (in view: work.prox_detect(verilog))
   u1.dat_l[2] (in view: work.prox_detect(verilog))
   u1.dat_l[1] (in view: work.prox_detect(verilog))
   u1.dat_l[0] (in view: work.prox_detect(verilog))
   u1.dat_valid (in view: work.prox_detect(verilog))
   u1.data_r[7] (in view: work.prox_detect(verilog))
   u1.data_r[6] (in view: work.prox_detect(verilog))
   u1.data_r[5] (in view: work.prox_detect(verilog))
   u1.data_r[4] (in view: work.prox_detect(verilog))
   u1.data_r[3] (in view: work.prox_detect(verilog))
   u1.data_r[2] (in view: work.prox_detect(verilog))
   u1.data_r[1] (in view: work.prox_detect(verilog))
   u1.data_r[0] (in view: work.prox_detect(verilog))
   u1.data_wr[7] (in view: work.prox_detect(verilog))
   u1.data_wr[6] (in view: work.prox_detect(verilog))
   u1.data_wr[4] (in view: work.prox_detect(verilog))
   u1.data_wr[3] (in view: work.prox_detect(verilog))
   u1.data_wr[2] (in view: work.prox_detect(verilog))
   u1.data_wr[1] (in view: work.prox_detect(verilog))
   u1.data_wr[0] (in view: work.prox_detect(verilog))
   u1.prox_dat[15] (in view: work.prox_detect(verilog))
   u1.prox_dat[14] (in view: work.prox_detect(verilog))
   u1.prox_dat[13] (in view: work.prox_detect(verilog))
   u1.prox_dat[12] (in view: work.prox_detect(verilog))
   u1.prox_dat[11] (in view: work.prox_detect(verilog))
   u1.prox_dat[10] (in view: work.prox_detect(verilog))
   u1.prox_dat[9] (in view: work.prox_detect(verilog))
   u1.prox_dat[8] (in view: work.prox_detect(verilog))
   u1.prox_dat[7] (in view: work.prox_detect(verilog))
   u1.prox_dat[6] (in view: work.prox_detect(verilog))
   u1.prox_dat[5] (in view: work.prox_detect(verilog))
   u1.prox_dat[4] (in view: work.prox_detect(verilog))
   u1.prox_dat[3] (in view: work.prox_detect(verilog))
   u1.prox_dat[2] (in view: work.prox_detect(verilog))
   u1.prox_dat[1] (in view: work.prox_detect(verilog))
   u1.prox_dat[0] (in view: work.prox_detect(verilog))
   u1.reg_addr[3] (in view: work.prox_detect(verilog))
   u1.reg_addr[2] (in view: work.prox_detect(verilog))
   u1.reg_addr[1] (in view: work.prox_detect(verilog))
   u1.reg_addr[0] (in view: work.prox_detect(verilog))
   u1.reg_data[3] (in view: work.prox_detect(verilog))
   u1.reg_data[2] (in view: work.prox_detect(verilog))
   u1.reg_data[1] (in view: work.prox_detect(verilog))
   u1.reg_data[0] (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_10 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_100 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_101 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_102 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_103 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_104 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_105 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_106 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_107 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_108 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_109 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_11 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_110 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_111 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_112 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_113 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_114 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_115 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_119 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_12 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_120 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_121 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_122 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_123 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_124 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_125 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_126 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_127 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_128 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_129 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_13 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_130 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_131 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_132 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_133 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_134 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_135 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_14 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_143 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_144 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_145 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_146 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_147 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_148 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_149 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_15 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_150 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_151 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_152 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_153 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_154 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_155 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_156 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_157 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_158 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_159 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_16 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_166 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_167 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_168 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_169 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_17 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_170 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_171 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_172 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_173 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_174 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_175 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_176 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_177 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_178 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_179 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_18 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_180 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_181 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_182 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_183 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_184 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_185 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_19 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_190 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_191 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_192 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_193 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_194 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_195 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_196 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_197 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_198 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_199 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_20 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_200 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_201 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_202 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_203 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_204 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_205 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_206 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_207 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_208 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_209 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_21 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_210 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_211 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_215 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_216 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_217 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_218 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_219 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_22 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_220 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_221 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_222 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_223 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_224 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_225 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_226 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_227 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_228 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_229 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_23 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_230 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_231 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_232 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_233 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_234 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_235 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_236 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_237 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_238 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_239 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_34 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_35 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_36 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_37 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_38 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_39 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_4 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_40 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_41 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_42 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_43 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_44 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_45 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_46 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_47 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_48 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_49 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_5 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_50 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_53 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_54 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_55 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_56 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_57 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_58 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_59 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_6 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_60 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_61 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_62 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_63 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_64 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_65 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_66 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_67 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_68 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_69 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_7 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_70 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_71 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_73 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_74 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_75 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_76 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_77 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_78 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_79 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_8 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_80 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_81 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_82 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_83 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_84 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_85 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_86 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_87 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_88 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_89 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_9 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_90 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_91 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_92 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_93 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_94 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_95 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_96 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_97 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_99 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_10 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_100 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_11 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_12 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_13 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_14 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_15 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_16 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_17 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_18 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_19 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_20 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_21 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_22 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_27 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_28 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_29 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_30 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_31 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_32 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_33 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_34 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_35 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_36 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_37 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_38 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_39 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_4 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_40 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_41 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_42 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_43 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_44 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_45 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_46 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_47 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_48 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_49 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_5 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_54 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_55 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_56 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_57 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_58 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_59 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_6 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_60 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_61 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_62 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_63 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_64 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_65 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_66 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_67 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_68 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_69 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_7 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_70 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_71 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_72 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_73 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_74 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_75 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_76 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_77 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_78 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_79 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_8 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_81 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_82 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_83 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_84 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_85 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_86 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_87 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_88 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_89 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_9 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_90 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_91 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_92 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_93 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_94 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_95 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_96 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_97 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_98 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_99 (in view: work.prox_detect(verilog))
   u2.prox_dat0[15] (in view: work.prox_detect(verilog))
   u2.prox_dat0[14] (in view: work.prox_detect(verilog))
   u2.prox_dat0[13] (in view: work.prox_detect(verilog))
   u2.prox_dat0[12] (in view: work.prox_detect(verilog))
   u2.prox_dat0[11] (in view: work.prox_detect(verilog))
   u2.prox_dat0[10] (in view: work.prox_detect(verilog))
   u2.prox_dat0[9] (in view: work.prox_detect(verilog))
   u2.prox_dat0[8] (in view: work.prox_detect(verilog))
   u2.prox_dat0[7] (in view: work.prox_detect(verilog))
   u2.prox_dat0[6] (in view: work.prox_detect(verilog))
   u2.prox_dat0[5] (in view: work.prox_detect(verilog))
   u2.prox_dat0[4] (in view: work.prox_detect(verilog))
   u2.prox_dat0[3] (in view: work.prox_detect(verilog))
   u2.prox_dat0[2] (in view: work.prox_detect(verilog))
   u2.prox_dat0[1] (in view: work.prox_detect(verilog))
   u2.prox_dat0[0] (in view: work.prox_detect(verilog))
   u2.prox_dat1[15] (in view: work.prox_detect(verilog))
   u2.prox_dat1[14] (in view: work.prox_detect(verilog))
   u2.prox_dat1[13] (in view: work.prox_detect(verilog))
   u2.prox_dat1[12] (in view: work.prox_detect(verilog))
   u2.prox_dat1[11] (in view: work.prox_detect(verilog))
   u2.prox_dat1[10] (in view: work.prox_detect(verilog))
   u2.prox_dat1[9] (in view: work.prox_detect(verilog))
   u2.prox_dat1[8] (in view: work.prox_detect(verilog))
   u2.prox_dat1[7] (in view: work.prox_detect(verilog))
   u2.prox_dat1[6] (in view: work.prox_detect(verilog))
   u2.prox_dat1[5] (in view: work.prox_detect(verilog))
   u2.prox_dat1[4] (in view: work.prox_detect(verilog))
   u2.prox_dat1[3] (in view: work.prox_detect(verilog))
   u2.prox_dat1[2] (in view: work.prox_detect(verilog))
   u2.prox_dat1[1] (in view: work.prox_detect(verilog))
   u2.prox_dat1[0] (in view: work.prox_detect(verilog))
   u2.prox_dat2[11] (in view: work.prox_detect(verilog))
   u2.prox_dat2[10] (in view: work.prox_detect(verilog))
   u2.prox_dat2[9] (in view: work.prox_detect(verilog))
   u3.data[15] (in view: work.prox_detect(verilog))
   u3.data[14] (in view: work.prox_detect(verilog))
   u3.data[13] (in view: work.prox_detect(verilog))
   u3.data[12] (in view: work.prox_detect(verilog))
   u3.data[11] (in view: work.prox_detect(verilog))
   u3.data[10] (in view: work.prox_detect(verilog))
   u3.data[9] (in view: work.prox_detect(verilog))
   u3.data[8] (in view: work.prox_detect(verilog))
   u3.data[7] (in view: work.prox_detect(verilog))
   u3.data[6] (in view: work.prox_detect(verilog))
   u3.data[5] (in view: work.prox_detect(verilog))
   u3.data[4] (in view: work.prox_detect(verilog))
   u3.data[3] (in view: work.prox_detect(verilog))
   u3.data[2] (in view: work.prox_detect(verilog))
   u3.data[1] (in view: work.prox_detect(verilog))
   u3.data[0] (in view: work.prox_detect(verilog))
   u5.buzz (in view: work.prox_detect(verilog))


Finished restoring hierarchy (Real Time elapsed 0h:03m:24s; CPU Time elapsed 0h:03m:23s; Memory used current: 384MB peak: 593MB)


Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:03m:24s; CPU Time elapsed 0h:03m:24s; Memory used current: 384MB peak: 593MB)


Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:03m:24s; CPU Time elapsed 0h:03m:24s; Memory used current: 384MB peak: 593MB)


Start Writing Netlists (Real Time elapsed 0h:03m:24s; CPU Time elapsed 0h:03m:24s; Memory used current: 306MB peak: 593MB)

Writing Analyst data base C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\synwork\prox_detect_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:03m:25s; CPU Time elapsed 0h:03m:24s; Memory used current: 368MB peak: 593MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1741322986> | Writing EDF file: C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.edi 
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1741322986> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:03m:26s; CPU Time elapsed 0h:03m:25s; Memory used current: 377MB peak: 593MB)


Finished Writing Netlists (Real Time elapsed 0h:03m:26s; CPU Time elapsed 0h:03m:25s; Memory used current: 377MB peak: 593MB)


Start final timing analysis (Real Time elapsed 0h:03m:26s; CPU Time elapsed 0h:03m:26s; Memory used current: 366MB peak: 593MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1741322986> | Found inferred clock prox_detect|clk with period 5.00ns. Please declare a user-defined clock on port clk.</font> 
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1741322986> | Found clock rpr0521rs_driver|clk_400khz_derived_clock with period 5.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1741322986> | Found clock segment_scan|clk_40khz_derived_clock with period 5.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1741322986> | Found clock rpr0521rs_driver|dat_valid_derived_clock with period 5.00ns  


<a name=timingReport24></a>##### START OF TIMING REPORT #####[</a>
# Timing report written on Fri Mar  7 12:49:46 2025
#


Top view:               prox_detect
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1741322986> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1741322986> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary25></a>Performance Summary</a>
*******************


Worst slack in design: -57.981

                                              Requested     Estimated     Requested     Estimated                 Clock                                                        Clock          
Starting Clock                                Frequency     Frequency     Period        Period        Slack       Type                                                         Group          
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                               200.0 MHz     16.2 MHz      5.000         61.549        -1.734      inferred                                                     (multiple)     
rpr0521rs_driver|clk_400khz_derived_clock     200.0 MHz     15.9 MHz      5.000         62.981        -57.981     derived (from prox_detect|clk)                               (multiple)     
rpr0521rs_driver|dat_valid_derived_clock      200.0 MHz     261.9 MHz     5.000         3.818         2.365       derived (from rpr0521rs_driver|clk_400khz_derived_clock)     (multiple)     
segment_scan|clk_40khz_derived_clock          200.0 MHz     15.9 MHz      5.000         62.981        2.805       derived (from prox_detect|clk)                               (multiple)     
System                                        200.0 MHz     NA            5.000         NA            NA          system                                                       system_clkgroup
==============================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





<a name=clockRelationships26></a>Clock Relationships</a>
*******************

Clocks                                                                                |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                   Ending                                     |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                            prox_detect|clk                            |  5.000       -1.735   |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  prox_detect|clk                            |  5.000       -56.549  |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  rpr0521rs_driver|clk_400khz_derived_clock  |  5.000       -1.530   |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  segment_scan|clk_40khz_derived_clock       |  5.000       -57.981  |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  rpr0521rs_driver|dat_valid_derived_clock   |  5.000       3.923    |  No paths    -      |  No paths    -      |  No paths    -    
segment_scan|clk_40khz_derived_clock       segment_scan|clk_40khz_derived_clock       |  5.000       2.805    |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|dat_valid_derived_clock   prox_detect|clk                            |  5.000       3.252    |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|dat_valid_derived_clock   rpr0521rs_driver|dat_valid_derived_clock   |  5.000       2.365    |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo27></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport28></a>Detailed Report for Clock: prox_detect|clk</a>
====================================



<a name=startingSlack29></a>Starting Points with Worst Slack</a>
********************************

                   Starting                                             Arrival           
Instance           Reference           Type        Pin     Net          Time        Slack 
                   Clock                                                                  
------------------------------------------------------------------------------------------
u5.u2.cnt_p[0]     prox_detect|clk     FD1S3AX     Q       cnt_p[0]     1.108       -1.734
u5.u1.cnt_p[0]     prox_detect|clk     FD1S3AX     Q       cnt_p[0]     1.108       -1.734
u5.u1.cnt_p[2]     prox_detect|clk     FD1S3AX     Q       cnt_p[2]     1.108       -1.592
u5.u2.cnt_p[1]     prox_detect|clk     FD1S3AX     Q       cnt_p[1]     1.044       -1.528
u5.u1.cnt_p[1]     prox_detect|clk     FD1S3AX     Q       cnt_p[1]     1.044       -1.528
u5.u2.cnt_p[2]     prox_detect|clk     FD1S3AX     Q       cnt_p[2]     1.044       -1.528
u5.u1.cnt_p[3]     prox_detect|clk     FD1S3AX     Q       cnt_p[3]     1.108       -1.449
u5.u1.cnt_p[4]     prox_detect|clk     FD1S3AX     Q       cnt_p[4]     1.108       -1.449
u5.u2.cnt_p[3]     prox_detect|clk     FD1S3AX     Q       cnt_p[3]     1.044       -1.385
u5.u2.cnt_p[4]     prox_detect|clk     FD1S3AX     Q       cnt_p[4]     1.044       -1.385
==========================================================================================


<a name=endingSlack30></a>Ending Points with Worst Slack</a>
******************************

                    Starting                                                   Required           
Instance            Reference           Type        Pin     Net                Time         Slack 
                    Clock                                                                         
--------------------------------------------------------------------------------------------------
u5.u1.cnt_p[35]     prox_detect|clk     FD1S3AX     D       un3_cnt_p[35]      4.894        -1.734
u5.u2.cnt_p[35]     prox_detect|clk     FD1S3AX     D       un16_cnt_p[35]     4.894        -1.734
u5.u2.cnt_p[33]     prox_detect|clk     FD1S3AX     D       un16_cnt_p[33]     4.894        -1.592
u5.u1.cnt_p[33]     prox_detect|clk     FD1S3AX     D       un3_cnt_p[33]      4.894        -1.592
u5.u1.cnt_p[34]     prox_detect|clk     FD1S3AX     D       un3_cnt_p[34]      4.894        -1.592
u5.u2.cnt_p[34]     prox_detect|clk     FD1S3AX     D       un16_cnt_p[34]     4.894        -1.592
u5.u1.cnt_p[31]     prox_detect|clk     FD1S3AX     D       un3_cnt_p[31]      4.894        -1.449
u5.u2.cnt_p[31]     prox_detect|clk     FD1S3AX     D       un16_cnt_p[31]     4.894        -1.449
u5.u2.cnt_p[32]     prox_detect|clk     FD1S3AX     D       un16_cnt_p[32]     4.894        -1.449
u5.u1.cnt_p[32]     prox_detect|clk     FD1S3AX     D       un3_cnt_p[32]      4.894        -1.449
==================================================================================================



<a name=worstPaths31></a>Worst Path Information</a>
<a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srr:srsfC:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srs:fp:123383:128963:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      6.629
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.734

    Number of logic level(s):                19
    Starting point:                          u5.u2.cnt_p[0] / Q
    Ending point:                            u5.u2.cnt_p[35] / D
    The start point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
u5.u2.cnt_p[0]                FD1S3AX     Q        Out     1.108     1.108 r     -         
cnt_p[0]                      Net         -        -       -         -           3         
u5.u2.un16_cnt_p_cry_0_0      CCU2D       A1       In      0.000     1.108 r     -         
u5.u2.un16_cnt_p_cry_0_0      CCU2D       COUT     Out     1.544     2.652 r     -         
un16_cnt_p_cry_0              Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_1_0      CCU2D       CIN      In      0.000     2.652 r     -         
u5.u2.un16_cnt_p_cry_1_0      CCU2D       COUT     Out     0.143     2.795 r     -         
un16_cnt_p_cry_2              Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_3_0      CCU2D       CIN      In      0.000     2.795 r     -         
u5.u2.un16_cnt_p_cry_3_0      CCU2D       COUT     Out     0.143     2.938 r     -         
un16_cnt_p_cry_4              Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_5_0      CCU2D       CIN      In      0.000     2.938 r     -         
u5.u2.un16_cnt_p_cry_5_0      CCU2D       COUT     Out     0.143     3.081 r     -         
un16_cnt_p_cry_6              Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_7_0      CCU2D       CIN      In      0.000     3.081 r     -         
u5.u2.un16_cnt_p_cry_7_0      CCU2D       COUT     Out     0.143     3.224 r     -         
un16_cnt_p_cry_8              Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_9_0      CCU2D       CIN      In      0.000     3.224 r     -         
u5.u2.un16_cnt_p_cry_9_0      CCU2D       COUT     Out     0.143     3.366 r     -         
un16_cnt_p_cry_10             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_11_0     CCU2D       CIN      In      0.000     3.366 r     -         
u5.u2.un16_cnt_p_cry_11_0     CCU2D       COUT     Out     0.143     3.509 r     -         
un16_cnt_p_cry_12             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_13_0     CCU2D       CIN      In      0.000     3.509 r     -         
u5.u2.un16_cnt_p_cry_13_0     CCU2D       COUT     Out     0.143     3.652 r     -         
un16_cnt_p_cry_14             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_15_0     CCU2D       CIN      In      0.000     3.652 r     -         
u5.u2.un16_cnt_p_cry_15_0     CCU2D       COUT     Out     0.143     3.795 r     -         
un16_cnt_p_cry_16             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_17_0     CCU2D       CIN      In      0.000     3.795 r     -         
u5.u2.un16_cnt_p_cry_17_0     CCU2D       COUT     Out     0.143     3.938 r     -         
un16_cnt_p_cry_18             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_19_0     CCU2D       CIN      In      0.000     3.938 r     -         
u5.u2.un16_cnt_p_cry_19_0     CCU2D       COUT     Out     0.143     4.080 r     -         
un16_cnt_p_cry_20             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_21_0     CCU2D       CIN      In      0.000     4.080 r     -         
u5.u2.un16_cnt_p_cry_21_0     CCU2D       COUT     Out     0.143     4.223 r     -         
un16_cnt_p_cry_22             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_23_0     CCU2D       CIN      In      0.000     4.223 r     -         
u5.u2.un16_cnt_p_cry_23_0     CCU2D       COUT     Out     0.143     4.366 r     -         
un16_cnt_p_cry_24             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_25_0     CCU2D       CIN      In      0.000     4.366 r     -         
u5.u2.un16_cnt_p_cry_25_0     CCU2D       COUT     Out     0.143     4.509 r     -         
un16_cnt_p_cry_26             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_27_0     CCU2D       CIN      In      0.000     4.509 r     -         
u5.u2.un16_cnt_p_cry_27_0     CCU2D       COUT     Out     0.143     4.652 r     -         
un16_cnt_p_cry_28             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_29_0     CCU2D       CIN      In      0.000     4.652 r     -         
u5.u2.un16_cnt_p_cry_29_0     CCU2D       COUT     Out     0.143     4.794 r     -         
un16_cnt_p_cry_30             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_31_0     CCU2D       CIN      In      0.000     4.794 r     -         
u5.u2.un16_cnt_p_cry_31_0     CCU2D       COUT     Out     0.143     4.937 r     -         
un16_cnt_p_cry_32             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_cry_33_0     CCU2D       CIN      In      0.000     4.937 r     -         
u5.u2.un16_cnt_p_cry_33_0     CCU2D       COUT     Out     0.143     5.080 r     -         
un16_cnt_p_cry_34             Net         -        -       -         -           1         
u5.u2.un16_cnt_p_s_35_0       CCU2D       CIN      In      0.000     5.080 r     -         
u5.u2.un16_cnt_p_s_35_0       CCU2D       S0       Out     1.549     6.629 r     -         
un16_cnt_p[35]                Net         -        -       -         -           1         
u5.u2.cnt_p[35]               FD1S3AX     D        In      0.000     6.629 r     -         
===========================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      6.629
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.734

    Number of logic level(s):                19
    Starting point:                          u5.u1.cnt_p[0] / Q
    Ending point:                            u5.u1.cnt_p[35] / D
    The start point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                           Pin      Pin               Arrival     No. of    
Name                         Type        Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------
u5.u1.cnt_p[0]               FD1S3AX     Q        Out     1.108     1.108 r     -         
cnt_p[0]                     Net         -        -       -         -           3         
u5.u1.un3_cnt_p_cry_0_0      CCU2D       A1       In      0.000     1.108 r     -         
u5.u1.un3_cnt_p_cry_0_0      CCU2D       COUT     Out     1.544     2.652 r     -         
un3_cnt_p_cry_0              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_1_0      CCU2D       CIN      In      0.000     2.652 r     -         
u5.u1.un3_cnt_p_cry_1_0      CCU2D       COUT     Out     0.143     2.795 r     -         
un3_cnt_p_cry_2              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_3_0      CCU2D       CIN      In      0.000     2.795 r     -         
u5.u1.un3_cnt_p_cry_3_0      CCU2D       COUT     Out     0.143     2.938 r     -         
un3_cnt_p_cry_4              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_5_0      CCU2D       CIN      In      0.000     2.938 r     -         
u5.u1.un3_cnt_p_cry_5_0      CCU2D       COUT     Out     0.143     3.081 r     -         
un3_cnt_p_cry_6              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_7_0      CCU2D       CIN      In      0.000     3.081 r     -         
u5.u1.un3_cnt_p_cry_7_0      CCU2D       COUT     Out     0.143     3.224 r     -         
un3_cnt_p_cry_8              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_9_0      CCU2D       CIN      In      0.000     3.224 r     -         
u5.u1.un3_cnt_p_cry_9_0      CCU2D       COUT     Out     0.143     3.366 r     -         
un3_cnt_p_cry_10             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_11_0     CCU2D       CIN      In      0.000     3.366 r     -         
u5.u1.un3_cnt_p_cry_11_0     CCU2D       COUT     Out     0.143     3.509 r     -         
un3_cnt_p_cry_12             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_13_0     CCU2D       CIN      In      0.000     3.509 r     -         
u5.u1.un3_cnt_p_cry_13_0     CCU2D       COUT     Out     0.143     3.652 r     -         
un3_cnt_p_cry_14             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_15_0     CCU2D       CIN      In      0.000     3.652 r     -         
u5.u1.un3_cnt_p_cry_15_0     CCU2D       COUT     Out     0.143     3.795 r     -         
un3_cnt_p_cry_16             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_17_0     CCU2D       CIN      In      0.000     3.795 r     -         
u5.u1.un3_cnt_p_cry_17_0     CCU2D       COUT     Out     0.143     3.938 r     -         
un3_cnt_p_cry_18             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_19_0     CCU2D       CIN      In      0.000     3.938 r     -         
u5.u1.un3_cnt_p_cry_19_0     CCU2D       COUT     Out     0.143     4.080 r     -         
un3_cnt_p_cry_20             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_21_0     CCU2D       CIN      In      0.000     4.080 r     -         
u5.u1.un3_cnt_p_cry_21_0     CCU2D       COUT     Out     0.143     4.223 r     -         
un3_cnt_p_cry_22             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_23_0     CCU2D       CIN      In      0.000     4.223 r     -         
u5.u1.un3_cnt_p_cry_23_0     CCU2D       COUT     Out     0.143     4.366 r     -         
un3_cnt_p_cry_24             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_25_0     CCU2D       CIN      In      0.000     4.366 r     -         
u5.u1.un3_cnt_p_cry_25_0     CCU2D       COUT     Out     0.143     4.509 r     -         
un3_cnt_p_cry_26             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_27_0     CCU2D       CIN      In      0.000     4.509 r     -         
u5.u1.un3_cnt_p_cry_27_0     CCU2D       COUT     Out     0.143     4.652 r     -         
un3_cnt_p_cry_28             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_29_0     CCU2D       CIN      In      0.000     4.652 r     -         
u5.u1.un3_cnt_p_cry_29_0     CCU2D       COUT     Out     0.143     4.794 r     -         
un3_cnt_p_cry_30             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_31_0     CCU2D       CIN      In      0.000     4.794 r     -         
u5.u1.un3_cnt_p_cry_31_0     CCU2D       COUT     Out     0.143     4.937 r     -         
un3_cnt_p_cry_32             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_33_0     CCU2D       CIN      In      0.000     4.937 r     -         
u5.u1.un3_cnt_p_cry_33_0     CCU2D       COUT     Out     0.143     5.080 r     -         
un3_cnt_p_cry_34             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_s_35_0       CCU2D       CIN      In      0.000     5.080 r     -         
u5.u1.un3_cnt_p_s_35_0       CCU2D       S0       Out     1.549     6.629 r     -         
un3_cnt_p[35]                Net         -        -       -         -           1         
u5.u1.cnt_p[35]              FD1S3AX     D        In      0.000     6.629 r     -         
==========================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      6.486
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.592

    Number of logic level(s):                18
    Starting point:                          u5.u1.cnt_p[2] / Q
    Ending point:                            u5.u1.cnt_p[35] / D
    The start point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                           Pin      Pin               Arrival     No. of    
Name                         Type        Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------
u5.u1.cnt_p[2]               FD1S3AX     Q        Out     1.108     1.108 r     -         
cnt_p[2]                     Net         -        -       -         -           3         
u5.u1.un3_cnt_p_cry_1_0      CCU2D       A1       In      0.000     1.108 r     -         
u5.u1.un3_cnt_p_cry_1_0      CCU2D       COUT     Out     1.544     2.652 r     -         
un3_cnt_p_cry_2              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_3_0      CCU2D       CIN      In      0.000     2.652 r     -         
u5.u1.un3_cnt_p_cry_3_0      CCU2D       COUT     Out     0.143     2.795 r     -         
un3_cnt_p_cry_4              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_5_0      CCU2D       CIN      In      0.000     2.795 r     -         
u5.u1.un3_cnt_p_cry_5_0      CCU2D       COUT     Out     0.143     2.938 r     -         
un3_cnt_p_cry_6              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_7_0      CCU2D       CIN      In      0.000     2.938 r     -         
u5.u1.un3_cnt_p_cry_7_0      CCU2D       COUT     Out     0.143     3.081 r     -         
un3_cnt_p_cry_8              Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_9_0      CCU2D       CIN      In      0.000     3.081 r     -         
u5.u1.un3_cnt_p_cry_9_0      CCU2D       COUT     Out     0.143     3.224 r     -         
un3_cnt_p_cry_10             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_11_0     CCU2D       CIN      In      0.000     3.224 r     -         
u5.u1.un3_cnt_p_cry_11_0     CCU2D       COUT     Out     0.143     3.366 r     -         
un3_cnt_p_cry_12             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_13_0     CCU2D       CIN      In      0.000     3.366 r     -         
u5.u1.un3_cnt_p_cry_13_0     CCU2D       COUT     Out     0.143     3.509 r     -         
un3_cnt_p_cry_14             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_15_0     CCU2D       CIN      In      0.000     3.509 r     -         
u5.u1.un3_cnt_p_cry_15_0     CCU2D       COUT     Out     0.143     3.652 r     -         
un3_cnt_p_cry_16             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_17_0     CCU2D       CIN      In      0.000     3.652 r     -         
u5.u1.un3_cnt_p_cry_17_0     CCU2D       COUT     Out     0.143     3.795 r     -         
un3_cnt_p_cry_18             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_19_0     CCU2D       CIN      In      0.000     3.795 r     -         
u5.u1.un3_cnt_p_cry_19_0     CCU2D       COUT     Out     0.143     3.938 r     -         
un3_cnt_p_cry_20             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_21_0     CCU2D       CIN      In      0.000     3.938 r     -         
u5.u1.un3_cnt_p_cry_21_0     CCU2D       COUT     Out     0.143     4.080 r     -         
un3_cnt_p_cry_22             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_23_0     CCU2D       CIN      In      0.000     4.080 r     -         
u5.u1.un3_cnt_p_cry_23_0     CCU2D       COUT     Out     0.143     4.223 r     -         
un3_cnt_p_cry_24             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_25_0     CCU2D       CIN      In      0.000     4.223 r     -         
u5.u1.un3_cnt_p_cry_25_0     CCU2D       COUT     Out     0.143     4.366 r     -         
un3_cnt_p_cry_26             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_27_0     CCU2D       CIN      In      0.000     4.366 r     -         
u5.u1.un3_cnt_p_cry_27_0     CCU2D       COUT     Out     0.143     4.509 r     -         
un3_cnt_p_cry_28             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_29_0     CCU2D       CIN      In      0.000     4.509 r     -         
u5.u1.un3_cnt_p_cry_29_0     CCU2D       COUT     Out     0.143     4.652 r     -         
un3_cnt_p_cry_30             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_31_0     CCU2D       CIN      In      0.000     4.652 r     -         
u5.u1.un3_cnt_p_cry_31_0     CCU2D       COUT     Out     0.143     4.794 r     -         
un3_cnt_p_cry_32             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_cry_33_0     CCU2D       CIN      In      0.000     4.794 r     -         
u5.u1.un3_cnt_p_cry_33_0     CCU2D       COUT     Out     0.143     4.937 r     -         
un3_cnt_p_cry_34             Net         -        -       -         -           1         
u5.u1.un3_cnt_p_s_35_0       CCU2D       CIN      In      0.000     4.937 r     -         
u5.u1.un3_cnt_p_s_35_0       CCU2D       S0       Out     1.549     6.486 r     -         
un3_cnt_p[35]                Net         -        -       -         -           1         
u5.u1.cnt_p[35]              FD1S3AX     D        In      0.000     6.486 r     -         
==========================================================================================




====================================
<a name=clockReport32></a>Detailed Report for Clock: rpr0521rs_driver|clk_400khz_derived_clock</a>
====================================



<a name=startingSlack33></a>Starting Points with Worst Slack</a>
********************************

                       Starting                                                                              Arrival            
Instance               Reference                                     Type        Pin     Net                 Time        Slack  
                       Clock                                                                                                    
--------------------------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[7]          1.256       -57.981
u1.ch1_dat[2]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[2]          1.244       -57.969
u1.ch1_dat[1]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[1]          1.236       -57.961
u1.ch0_dat_0_rep1      rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_0_rep1      1.188       -57.913
u1.ch1_dat_fast[0]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat_fast[0]     0.972       -57.840
u1.ch1_dat_fast[5]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat_fast[5]     0.972       -57.840
u1.ch1_dat[8]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[8]          1.256       -57.838
u1.ch1_dat[9]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[9]          1.256       -57.838
u1.ch0_dat_fast[2]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_fast[2]     1.108       -57.833
u1.ch0_dat_1_rep1      rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_1_rep1      1.204       -57.786
================================================================================================================================


<a name=endingSlack34></a>Ending Points with Worst Slack</a>
******************************

                     Starting                                                                              Required            
Instance             Reference                                     Type        Pin     Net                 Time         Slack  
                     Clock                                                                                                     
-------------------------------------------------------------------------------------------------------------------------------
u3.data[8]           rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[8]          5.089        -57.981
u3.data[12]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[12]         5.462        -57.259
u3.data[9]           rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[9]          5.462        -57.048
u3.data[13]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[13]         5.089        -56.838
u3.data[11]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[11]         5.089        -56.773
u3.data[14]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_N_7_0_i        5.089        -56.754
led_reg              rpr0521rs_driver|clk_400khz_derived_clock     FD1S3AX     D       led_reg6_i          4.894        -56.549
u3.data[10]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[10]         5.462        -56.028
u1.cnt_delay[23]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       cnt_delay_s[23]     9.894        -1.530 
u1.cnt_delay[21]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       cnt_delay_s[21]     9.894        -1.387 
===============================================================================================================================



<a name=worstPaths35></a>Worst Path Information</a>
<a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srr:srsfC:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srs:fp:147717:169605:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      63.070
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -57.981

    Number of logic level(s):                63
    Starting point:                          u1.ch1_dat[7] / Q
    Ending point:                            u3.data[8] / D
    The start point is clocked by            rpr0521rs_driver|clk_400khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                                               Pin      Pin                Arrival      No. of    
Name                                            Type         Name     Dir     Delay      Time         Fan Out(s)
----------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]                                   FD1P3AX      Q        Out     1.256      1.256 r      -         
ch1_dat[7]                                      Net          -        -       -          -            14        
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        A1       In      0.000      1.256 r      -         
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        COUT     Out     1.544      2.800 r      -         
un1_ch1_dat_1_cry_7                             Net          -        -       -          -            1         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        CIN      In      0.000      2.800 r      -         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        S0       Out     1.685      4.485 r      -         
un1_ch1_dat_1[8]                                Net          -        -       -          -            3         
u2.un1_lux_1_d1_39                              ORCALUT4     B        In      0.000      4.485 r      -         
u2.un1_lux_1_d1_39                              ORCALUT4     Z        Out     1.017      5.502 r      -         
un1_lux_1_d1_39                                 Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        C1       In      0.000      5.502 r      -         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        COUT     Out     1.544      7.047 r      -         
un1_lux_1_s0_m1_0_cry_8                         Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        CIN      In      0.000      7.047 r      -         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        COUT     Out     0.143      7.189 r      -         
un1_lux_1_s0_m1_0_cry_10                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        CIN      In      0.000      7.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        COUT     Out     0.143      7.332 r      -         
un1_lux_1_s0_m1_0_cry_12                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        CIN      In      0.000      7.332 r      -         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        COUT     Out     0.143      7.475 r      -         
un1_lux_1_s0_m1_0_cry_14                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        CIN      In      0.000      7.475 r      -         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        COUT     Out     0.143      7.618 r      -         
un1_lux_1_s0_m1_0_cry_16                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        CIN      In      0.000      7.618 r      -         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        COUT     Out     0.143      7.761 r      -         
un1_lux_1_s0_m1_0_cry_18                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        CIN      In      0.000      7.761 r      -         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        COUT     Out     0.143      7.903 r      -         
un1_lux_1_s0_m1_0_cry_20                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        CIN      In      0.000      7.903 r      -         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        COUT     Out     0.143      8.046 r      -         
un1_lux_1_s0_m1_0_cry_22                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        CIN      In      0.000      8.046 r      -         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        COUT     Out     0.143      8.189 r      -         
un1_lux_1_s0_m1_0_cry_24                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        CIN      In      0.000      8.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        S0       Out     1.621      9.810 r      -         
un1_lux_1_s0_m1_0_cry_25_0_S0                   Net          -        -       -          -            2         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     A        In      0.000      9.810 r      -         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     Z        Out     1.193      11.003 r     -         
un1_lux_1_s0_m1[27]                             Net          -        -       -          -            4         
u2.u1.shift_reg_34_a0_sx_RNO[34]                ORCALUT4     B        In      0.000      11.003 r     -         
u2.u1.shift_reg_34_a0_sx_RNO[34]                ORCALUT4     Z        Out     1.017      12.020 r     -         
un1_lux_1_s0_rn_0[27]                           Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_sx[34]                    ORCALUT4     B        In      0.000      12.020 r     -         
u2.u1.shift_reg_34_a0_sx[34]                    ORCALUT4     Z        Out     1.017      13.036 r     -         
shift_reg_34_a0_sx[34]                          Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_x1[34]                    ORCALUT4     A        In      0.000      13.036 r     -         
u2.u1.shift_reg_34_a0_x1[34]                    ORCALUT4     Z        Out     1.017      14.053 f     -         
shift_reg_34_a0_x1[34]                          Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_x1_RNI2H2E7[34]           ORCALUT4     A        In      0.000      14.053 f     -         
u2.u1.shift_reg_34_a0_x1_RNI2H2E7[34]           ORCALUT4     Z        Out     1.193      15.246 f     -         
shift_reg_34_a0_x1_RNI2H2E7[34]                 Net          -        -       -          -            4         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     A        In      0.000      15.246 f     -         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     Z        Out     1.265      16.511 r     -         
CO0_118                                         Net          -        -       -          -            8         
u2.u1.shift_reg_41[33]                          ORCALUT4     B        In      0.000      16.511 r     -         
u2.u1.shift_reg_41[33]                          ORCALUT4     Z        Out     1.289      17.800 r     -         
shift_reg_41[33]                                Net          -        -       -          -            12        
u2.u1.shift_reg_64_i_i_a2_N_3L3                 ORCALUT4     B        In      0.000      17.800 r     -         
u2.u1.shift_reg_64_i_i_a2_N_3L3                 ORCALUT4     Z        Out     1.017      18.816 r     -         
shift_reg_64_i_i_a2_N_3L3                       Net          -        -       -          -            1         
u2.u1.shift_reg_64_i_i_a2_N_4L5                 ORCALUT4     D        In      0.000      18.816 r     -         
u2.u1.shift_reg_64_i_i_a2_N_4L5                 ORCALUT4     Z        Out     1.017      19.833 r     -         
shift_reg_64_i_i_a2_N_4L5                       Net          -        -       -          -            1         
u2.u1.shift_reg_64_i_i_a2[37]                   ORCALUT4     D        In      0.000      19.833 r     -         
u2.u1.shift_reg_64_i_i_a2[37]                   ORCALUT4     Z        Out     1.233      21.066 r     -         
ANB1_112                                        Net          -        -       -          -            6         
u2.u1.shift_reg_74[39]                          ORCALUT4     A        In      0.000      21.066 r     -         
u2.u1.shift_reg_74[39]                          ORCALUT4     Z        Out     1.249      22.315 r     -         
shift_reg_74[39]                                Net          -        -       -          -            7         
u2.u1.shift_reg_87_N_2L1                        ORCALUT4     B        In      0.000      22.315 r     -         
u2.u1.shift_reg_87_N_2L1                        ORCALUT4     Z        Out     1.017      23.332 r     -         
shift_reg_87_N_2L1                              Net          -        -       -          -            1         
u2.u1.shift_reg_87[38]                          ORCALUT4     C        In      0.000      23.332 r     -         
u2.u1.shift_reg_87[38]                          ORCALUT4     Z        Out     1.193      24.524 r     -         
shift_reg_87[38]                                Net          -        -       -          -            4         
u2.u1.shift_reg_87_0_a2_0_a2_RNI2T0CV[37]       ORCALUT4     C        In      0.000      24.524 r     -         
u2.u1.shift_reg_87_0_a2_0_a2_RNI2T0CV[37]       ORCALUT4     Z        Out     1.225      25.749 r     -         
CO0_101                                         Net          -        -       -          -            5         
u2.u1.shift_reg_116_N_2L1                       ORCALUT4     A        In      0.000      25.749 r     -         
u2.u1.shift_reg_116_N_2L1                       ORCALUT4     Z        Out     1.017      26.766 r     -         
shift_reg_116_N_2L1                             Net          -        -       -          -            1         
u2.u1.shift_reg_116_mb[42]                      ORCALUT4     B        In      0.000      26.766 r     -         
u2.u1.shift_reg_116_mb[42]                      ORCALUT4     Z        Out     1.233      27.999 f     -         
shift_reg_116[42]                               Net          -        -       -          -            6         
u2.u1.shift_reg_116_RNI3BOOH1[43]               ORCALUT4     C        In      0.000      27.999 f     -         
u2.u1.shift_reg_116_RNI3BOOH1[43]               ORCALUT4     Z        Out     1.017      29.016 r     -         
SUM1_75_3_N_4L6_N_2L1_sx                        Net          -        -       -          -            1         
u2.u1.shift_reg_116_RNID6ROO2[43]               ORCALUT4     B        In      0.000      29.016 r     -         
u2.u1.shift_reg_116_RNID6ROO2[43]               ORCALUT4     Z        Out     1.017      30.032 f     -         
shift_reg_116_RNID6ROO2[43]                     Net          -        -       -          -            1         
u2.u1.shift_reg_116_i_0_RNIIMJ2Q5[41]           ORCALUT4     D        In      0.000      30.032 f     -         
u2.u1.shift_reg_116_i_0_RNIIMJ2Q5[41]           ORCALUT4     Z        Out     1.017      31.049 r     -         
shift_reg_116_i_0_RNIIMJ2Q5[41]                 Net          -        -       -          -            1         
u2.u1.shift_reg_132_RNIAJNCLO2[43]              ORCALUT4     C        In      0.000      31.049 r     -         
u2.u1.shift_reg_132_RNIAJNCLO2[43]              ORCALUT4     Z        Out     1.017      32.066 r     -         
shift_reg_132_RNIAJNCLO2[43]                    Net          -        -       -          -            1         
u2.u1.shift_reg_151_RNI345SMO2[46]              ORCALUT4     A        In      0.000      32.066 r     -         
u2.u1.shift_reg_151_RNI345SMO2[46]              ORCALUT4     Z        Out     1.225      33.291 r     -         
CO0_82                                          Net          -        -       -          -            5         
u2.u1.shift_reg_167[46]                         PFUMX        C0       In      0.000      33.291 r     -         
u2.u1.shift_reg_167[46]                         PFUMX        Z        Out     1.089      34.380 r     -         
shift_reg_167[46]                               Net          -        -       -          -            4         
u2.u1.shift_reg_167_i_0_RNI13OQV[45]            ORCALUT4     C        In      0.000      34.380 r     -         
u2.u1.shift_reg_167_i_0_RNI13OQV[45]            ORCALUT4     Z        Out     1.277      35.657 r     -         
CO0_76                                          Net          -        -       -          -            10        
u2.u1.shift_reg_189_RNIIGG2B1_3[51]             ORCALUT4     B        In      0.000      35.657 r     -         
u2.u1.shift_reg_189_RNIIGG2B1_3[51]             ORCALUT4     Z        Out     1.225      36.881 r     -         
CO0_72                                          Net          -        -       -          -            5         
u2.u1.shift_reg_227_i_i_a2_0[49]                ORCALUT4     B        In      0.000      36.881 r     -         
u2.u1.shift_reg_227_i_i_a2_0[49]                ORCALUT4     Z        Out     1.249      38.130 r     -         
shift_reg_227_i_i_a2_0[49]                      Net          -        -       -          -            7         
u2.u1.shift_reg_249_N_2L1_0                     ORCALUT4     D        In      0.000      38.130 r     -         
u2.u1.shift_reg_249_N_2L1_0                     ORCALUT4     Z        Out     1.017      39.147 r     -         
shift_reg_249_N_2L1_0                           Net          -        -       -          -            1         
u2.u1.shift_reg_249[51]                         ORCALUT4     D        In      0.000      39.147 r     -         
u2.u1.shift_reg_249[51]                         ORCALUT4     Z        Out     1.233      40.380 r     -         
shift_reg_249[51]                               Net          -        -       -          -            6         
u2.u1.shift_reg_271_1[50]                       ORCALUT4     C        In      0.000      40.380 r     -         
u2.u1.shift_reg_271_1[50]                       ORCALUT4     Z        Out     1.153      41.533 r     -         
shift_reg_271_1[50]                             Net          -        -       -          -            3         
u2.u1.shift_reg_271_1_RNI2LOLQL_0[50]           ORCALUT4     D        In      0.000      41.533 r     -         
u2.u1.shift_reg_271_1_RNI2LOLQL_0[50]           ORCALUT4     Z        Out     1.017      42.549 r     -         
CO2_45_N_3L4_sx                                 Net          -        -       -          -            1         
u2.u1.shift_reg_271_i_i_a2_RNIABEM3N_0[49]      ORCALUT4     B        In      0.000      42.549 r     -         
u2.u1.shift_reg_271_i_i_a2_RNIABEM3N_0[49]      ORCALUT4     Z        Out     1.017      43.566 f     -         
shift_reg_271_i_i_a2_RNIABEM3N_0[49]            Net          -        -       -          -            1         
u2.u1.shift_reg_249_RNIC7TB261_0[51]            ORCALUT4     B        In      0.000      43.566 f     -         
u2.u1.shift_reg_249_RNIC7TB261_0[51]            ORCALUT4     Z        Out     1.017      44.583 r     -         
shift_reg_249_RNIC7TB261_0[51]                  Net          -        -       -          -            1         
u2.u1.shift_reg_296_i_i_a2_0_RNIIICACJ2[53]     ORCALUT4     A        In      0.000      44.583 r     -         
u2.u1.shift_reg_296_i_i_a2_0_RNIIICACJ2[53]     ORCALUT4     Z        Out     1.249      45.832 r     -         
CO2_41                                          Net          -        -       -          -            7         
u2.u1.shift_reg_324_i_i_a2_RNINHT34C1[57]       ORCALUT4     B        In      0.000      45.832 r     -         
u2.u1.shift_reg_324_i_i_a2_RNINHT34C1[57]       ORCALUT4     Z        Out     1.017      46.849 r     -         
shift_reg_324_i_i_a2_RNINHT34C1[57]             Net          -        -       -          -            1         
u2.u1.shift_reg_299_RNI3MG40C3[58]              ORCALUT4     C        In      0.000      46.849 r     -         
u2.u1.shift_reg_299_RNI3MG40C3[58]              ORCALUT4     Z        Out     1.289      48.137 r     -         
CO0_33                                          Net          -        -       -          -            12        
u2.u1.shift_reg_296_RNI3VO18V1[55]              ORCALUT4     A        In      0.000      48.137 r     -         
u2.u1.shift_reg_296_RNI3VO18V1[55]              ORCALUT4     Z        Out     1.017      49.154 r     -         
shift_reg_296_RNI3VO18V1[55]                    Net          -        -       -          -            1         
u2.u1.shift_reg_324_RNI9ROMBB1[58]              ORCALUT4     C        In      0.000      49.154 r     -         
u2.u1.shift_reg_324_RNI9ROMBB1[58]              ORCALUT4     Z        Out     1.265      50.419 r     -         
CO0_25                                          Net          -        -       -          -            8         
u2.u1.shift_reg_374[58]                         ORCALUT4     B        In      0.000      50.419 r     -         
u2.u1.shift_reg_374[58]                         ORCALUT4     Z        Out     1.233      51.652 r     -         
shift_reg_374[58]                               Net          -        -       -          -            6         
u2.u1.shift_reg_374_i_i_a2_RNIDF71AS2_2[57]     ORCALUT4     D        In      0.000      51.652 r     -         
u2.u1.shift_reg_374_i_i_a2_RNIDF71AS2_2[57]     ORCALUT4     Z        Out     1.297      52.949 r     -         
CO0_20                                          Net          -        -       -          -            13        
u2.u1.shift_reg_405_RNI3F6JKS2[63]              ORCALUT4     B        In      0.000      52.949 r     -         
u2.u1.shift_reg_405_RNI3F6JKS2[63]              ORCALUT4     Z        Out     1.301      54.249 r     -         
un1_shift_reg_axb0_1                            Net          -        -       -          -            14        
u2.u1.shift_reg_433_RNIRUVH623_1[62]            ORCALUT4     C        In      0.000      54.249 r     -         
u2.u1.shift_reg_433_RNIRUVH623_1[62]            ORCALUT4     Z        Out     1.017      55.266 r     -         
shift_reg_433_RNIRUVH623_1[62]                  Net          -        -       -          -            1         
u2.u1.shift_reg_405_RNII8I21Q[62]               ORCALUT4     B        In      0.000      55.266 r     -         
u2.u1.shift_reg_405_RNII8I21Q[62]               ORCALUT4     Z        Out     1.225      56.491 r     -         
un1_shift_reg_axb0                              Net          -        -       -          -            5         
u2.u1._l31\.un1_shift_reg_ac0_5                 ORCALUT4     C        In      0.000      56.491 r     -         
u2.u1._l31\.un1_shift_reg_ac0_5                 ORCALUT4     Z        Out     1.193      57.684 f     -         
bcd_code_1_0[29]                                Net          -        -       -          -            4         
u2.u1.bcd_code[31]                              ORCALUT4     C        In      0.000      57.684 f     -         
u2.u1.bcd_code[31]                              ORCALUT4     Z        Out     1.273      58.957 r     -         
lux_data[31]                                    Net          -        -       -          -            9         
u3.data_12_1_am_N_3L3_0_x0                      ORCALUT4     B        In      0.000      58.957 r     -         
u3.data_12_1_am_N_3L3_0_x0                      ORCALUT4     Z        Out     1.017      59.973 f     -         
data_12_1_am_N_3L3_0_x0                         Net          -        -       -          -            1         
u3.data_12_1_am_N_3L3_0                         PFUMX        BLUT     In      0.000      59.973 f     -         
u3.data_12_1_am_N_3L3_0                         PFUMX        Z        Out     0.214      60.188 f     -         
data_12_1_am_N_3L3_0                            Net          -        -       -          -            1         
u3.data_12_1_am[8]                              ORCALUT4     B        In      0.000      60.188 f     -         
u3.data_12_1_am[8]                              ORCALUT4     Z        Out     1.017      61.204 r     -         
data_12_1_am[8]                                 Net          -        -       -          -            1         
u3.data_12_1[8]                                 PFUMX        BLUT     In      0.000      61.204 r     -         
u3.data_12_1[8]                                 PFUMX        Z        Out     -0.033     61.171 r     -         
N_523                                           Net          -        -       -          -            1         
u3.data_12_3[8]                                 L6MUX21      D1       In      0.000      61.171 r     -         
u3.data_12_3[8]                                 L6MUX21      Z        Out     0.265      61.436 r     -         
N_537                                           Net          -        -       -          -            1         
u3.data_12_7_1[8]                               ORCALUT4     A        In      0.000      61.436 r     -         
u3.data_12_7_1[8]                               ORCALUT4     Z        Out     1.017      62.453 f     -         
data_12_7_1[8]                                  Net          -        -       -          -            1         
u3.data_12_7[8]                                 ORCALUT4     D        In      0.000      62.453 f     -         
u3.data_12_7[8]                                 ORCALUT4     Z        Out     0.617      63.070 r     -         
data_12[8]                                      Net          -        -       -          -            1         
u3.data[8]                                      FD1P3AX      D        In      0.000      63.070 r     -         
================================================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      63.070
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -57.981

    Number of logic level(s):                63
    Starting point:                          u1.ch1_dat[7] / Q
    Ending point:                            u3.data[8] / D
    The start point is clocked by            rpr0521rs_driver|clk_400khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                                               Pin      Pin                Arrival      No. of    
Name                                            Type         Name     Dir     Delay      Time         Fan Out(s)
----------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]                                   FD1P3AX      Q        Out     1.256      1.256 r      -         
ch1_dat[7]                                      Net          -        -       -          -            14        
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        A1       In      0.000      1.256 r      -         
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        COUT     Out     1.544      2.800 r      -         
un1_ch1_dat_1_cry_7                             Net          -        -       -          -            1         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        CIN      In      0.000      2.800 r      -         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        COUT     Out     0.143      2.943 r      -         
un1_ch1_dat_1_cry_9                             Net          -        -       -          -            1         
u2.un1_ch1_dat_1_cry_10_0                       CCU2D        CIN      In      0.000      2.943 r      -         
u2.un1_ch1_dat_1_cry_10_0                       CCU2D        S0       Out     1.685      4.628 r      -         
un1_ch1_dat_1[10]                               Net          -        -       -          -            3         
u2.un1_lux_1_d1_49                              ORCALUT4     B        In      0.000      4.628 r      -         
u2.un1_lux_1_d1_49                              ORCALUT4     Z        Out     1.017      5.645 r      -         
un1_lux_1_d1_49                                 Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        C1       In      0.000      5.645 r      -         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        COUT     Out     1.544      7.189 r      -         
un1_lux_1_s0_m1_0_cry_10                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        CIN      In      0.000      7.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        COUT     Out     0.143      7.332 r      -         
un1_lux_1_s0_m1_0_cry_12                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        CIN      In      0.000      7.332 r      -         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        COUT     Out     0.143      7.475 r      -         
un1_lux_1_s0_m1_0_cry_14                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        CIN      In      0.000      7.475 r      -         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        COUT     Out     0.143      7.618 r      -         
un1_lux_1_s0_m1_0_cry_16                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        CIN      In      0.000      7.618 r      -         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        COUT     Out     0.143      7.761 r      -         
un1_lux_1_s0_m1_0_cry_18                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        CIN      In      0.000      7.761 r      -         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        COUT     Out     0.143      7.903 r      -         
un1_lux_1_s0_m1_0_cry_20                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        CIN      In      0.000      7.903 r      -         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        COUT     Out     0.143      8.046 r      -         
un1_lux_1_s0_m1_0_cry_22                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        CIN      In      0.000      8.046 r      -         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        COUT     Out     0.143      8.189 r      -         
un1_lux_1_s0_m1_0_cry_24                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        CIN      In      0.000      8.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        S0       Out     1.621      9.810 r      -         
un1_lux_1_s0_m1_0_cry_25_0_S0                   Net          -        -       -          -            2         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     A        In      0.000      9.810 r      -         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     Z        Out     1.193      11.003 r     -         
un1_lux_1_s0_m1[27]                             Net          -        -       -          -            4         
u2.u1.shift_reg_34_a0_sx_RNO[34]                ORCALUT4     B        In      0.000      11.003 r     -         
u2.u1.shift_reg_34_a0_sx_RNO[34]                ORCALUT4     Z        Out     1.017      12.020 r     -         
un1_lux_1_s0_rn_0[27]                           Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_sx[34]                    ORCALUT4     B        In      0.000      12.020 r     -         
u2.u1.shift_reg_34_a0_sx[34]                    ORCALUT4     Z        Out     1.017      13.036 r     -         
shift_reg_34_a0_sx[34]                          Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_x1[34]                    ORCALUT4     A        In      0.000      13.036 r     -         
u2.u1.shift_reg_34_a0_x1[34]                    ORCALUT4     Z        Out     1.017      14.053 f     -         
shift_reg_34_a0_x1[34]                          Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_x1_RNI2H2E7[34]           ORCALUT4     A        In      0.000      14.053 f     -         
u2.u1.shift_reg_34_a0_x1_RNI2H2E7[34]           ORCALUT4     Z        Out     1.193      15.246 f     -         
shift_reg_34_a0_x1_RNI2H2E7[34]                 Net          -        -       -          -            4         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     A        In      0.000      15.246 f     -         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     Z        Out     1.265      16.511 r     -         
CO0_118                                         Net          -        -       -          -            8         
u2.u1.shift_reg_41[33]                          ORCALUT4     B        In      0.000      16.511 r     -         
u2.u1.shift_reg_41[33]                          ORCALUT4     Z        Out     1.289      17.800 r     -         
shift_reg_41[33]                                Net          -        -       -          -            12        
u2.u1.shift_reg_64_i_i_a2_N_3L3                 ORCALUT4     B        In      0.000      17.800 r     -         
u2.u1.shift_reg_64_i_i_a2_N_3L3                 ORCALUT4     Z        Out     1.017      18.816 r     -         
shift_reg_64_i_i_a2_N_3L3                       Net          -        -       -          -            1         
u2.u1.shift_reg_64_i_i_a2_N_4L5                 ORCALUT4     D        In      0.000      18.816 r     -         
u2.u1.shift_reg_64_i_i_a2_N_4L5                 ORCALUT4     Z        Out     1.017      19.833 r     -         
shift_reg_64_i_i_a2_N_4L5                       Net          -        -       -          -            1         
u2.u1.shift_reg_64_i_i_a2[37]                   ORCALUT4     D        In      0.000      19.833 r     -         
u2.u1.shift_reg_64_i_i_a2[37]                   ORCALUT4     Z        Out     1.233      21.066 r     -         
ANB1_112                                        Net          -        -       -          -            6         
u2.u1.shift_reg_74[39]                          ORCALUT4     A        In      0.000      21.066 r     -         
u2.u1.shift_reg_74[39]                          ORCALUT4     Z        Out     1.249      22.315 r     -         
shift_reg_74[39]                                Net          -        -       -          -            7         
u2.u1.shift_reg_87_N_2L1                        ORCALUT4     B        In      0.000      22.315 r     -         
u2.u1.shift_reg_87_N_2L1                        ORCALUT4     Z        Out     1.017      23.332 r     -         
shift_reg_87_N_2L1                              Net          -        -       -          -            1         
u2.u1.shift_reg_87[38]                          ORCALUT4     C        In      0.000      23.332 r     -         
u2.u1.shift_reg_87[38]                          ORCALUT4     Z        Out     1.193      24.524 r     -         
shift_reg_87[38]                                Net          -        -       -          -            4         
u2.u1.shift_reg_87_0_a2_0_a2_RNI2T0CV[37]       ORCALUT4     C        In      0.000      24.524 r     -         
u2.u1.shift_reg_87_0_a2_0_a2_RNI2T0CV[37]       ORCALUT4     Z        Out     1.225      25.749 r     -         
CO0_101                                         Net          -        -       -          -            5         
u2.u1.shift_reg_116_N_2L1                       ORCALUT4     A        In      0.000      25.749 r     -         
u2.u1.shift_reg_116_N_2L1                       ORCALUT4     Z        Out     1.017      26.766 r     -         
shift_reg_116_N_2L1                             Net          -        -       -          -            1         
u2.u1.shift_reg_116_mb[42]                      ORCALUT4     B        In      0.000      26.766 r     -         
u2.u1.shift_reg_116_mb[42]                      ORCALUT4     Z        Out     1.233      27.999 f     -         
shift_reg_116[42]                               Net          -        -       -          -            6         
u2.u1.shift_reg_116_RNI3BOOH1[43]               ORCALUT4     C        In      0.000      27.999 f     -         
u2.u1.shift_reg_116_RNI3BOOH1[43]               ORCALUT4     Z        Out     1.017      29.016 r     -         
SUM1_75_3_N_4L6_N_2L1_sx                        Net          -        -       -          -            1         
u2.u1.shift_reg_116_RNID6ROO2[43]               ORCALUT4     B        In      0.000      29.016 r     -         
u2.u1.shift_reg_116_RNID6ROO2[43]               ORCALUT4     Z        Out     1.017      30.032 f     -         
shift_reg_116_RNID6ROO2[43]                     Net          -        -       -          -            1         
u2.u1.shift_reg_116_i_0_RNIIMJ2Q5[41]           ORCALUT4     D        In      0.000      30.032 f     -         
u2.u1.shift_reg_116_i_0_RNIIMJ2Q5[41]           ORCALUT4     Z        Out     1.017      31.049 r     -         
shift_reg_116_i_0_RNIIMJ2Q5[41]                 Net          -        -       -          -            1         
u2.u1.shift_reg_132_RNIAJNCLO2[43]              ORCALUT4     C        In      0.000      31.049 r     -         
u2.u1.shift_reg_132_RNIAJNCLO2[43]              ORCALUT4     Z        Out     1.017      32.066 r     -         
shift_reg_132_RNIAJNCLO2[43]                    Net          -        -       -          -            1         
u2.u1.shift_reg_151_RNI345SMO2[46]              ORCALUT4     A        In      0.000      32.066 r     -         
u2.u1.shift_reg_151_RNI345SMO2[46]              ORCALUT4     Z        Out     1.225      33.291 r     -         
CO0_82                                          Net          -        -       -          -            5         
u2.u1.shift_reg_167[46]                         PFUMX        C0       In      0.000      33.291 r     -         
u2.u1.shift_reg_167[46]                         PFUMX        Z        Out     1.089      34.380 r     -         
shift_reg_167[46]                               Net          -        -       -          -            4         
u2.u1.shift_reg_167_i_0_RNI13OQV[45]            ORCALUT4     C        In      0.000      34.380 r     -         
u2.u1.shift_reg_167_i_0_RNI13OQV[45]            ORCALUT4     Z        Out     1.277      35.657 r     -         
CO0_76                                          Net          -        -       -          -            10        
u2.u1.shift_reg_189_RNIIGG2B1_3[51]             ORCALUT4     B        In      0.000      35.657 r     -         
u2.u1.shift_reg_189_RNIIGG2B1_3[51]             ORCALUT4     Z        Out     1.225      36.881 r     -         
CO0_72                                          Net          -        -       -          -            5         
u2.u1.shift_reg_227_i_i_a2_0[49]                ORCALUT4     B        In      0.000      36.881 r     -         
u2.u1.shift_reg_227_i_i_a2_0[49]                ORCALUT4     Z        Out     1.249      38.130 r     -         
shift_reg_227_i_i_a2_0[49]                      Net          -        -       -          -            7         
u2.u1.shift_reg_249_N_2L1_0                     ORCALUT4     D        In      0.000      38.130 r     -         
u2.u1.shift_reg_249_N_2L1_0                     ORCALUT4     Z        Out     1.017      39.147 r     -         
shift_reg_249_N_2L1_0                           Net          -        -       -          -            1         
u2.u1.shift_reg_249[51]                         ORCALUT4     D        In      0.000      39.147 r     -         
u2.u1.shift_reg_249[51]                         ORCALUT4     Z        Out     1.233      40.380 r     -         
shift_reg_249[51]                               Net          -        -       -          -            6         
u2.u1.shift_reg_271_1[50]                       ORCALUT4     C        In      0.000      40.380 r     -         
u2.u1.shift_reg_271_1[50]                       ORCALUT4     Z        Out     1.153      41.533 r     -         
shift_reg_271_1[50]                             Net          -        -       -          -            3         
u2.u1.shift_reg_271_1_RNI2LOLQL_0[50]           ORCALUT4     D        In      0.000      41.533 r     -         
u2.u1.shift_reg_271_1_RNI2LOLQL_0[50]           ORCALUT4     Z        Out     1.017      42.549 r     -         
CO2_45_N_3L4_sx                                 Net          -        -       -          -            1         
u2.u1.shift_reg_271_i_i_a2_RNIABEM3N_0[49]      ORCALUT4     B        In      0.000      42.549 r     -         
u2.u1.shift_reg_271_i_i_a2_RNIABEM3N_0[49]      ORCALUT4     Z        Out     1.017      43.566 f     -         
shift_reg_271_i_i_a2_RNIABEM3N_0[49]            Net          -        -       -          -            1         
u2.u1.shift_reg_249_RNIC7TB261_0[51]            ORCALUT4     B        In      0.000      43.566 f     -         
u2.u1.shift_reg_249_RNIC7TB261_0[51]            ORCALUT4     Z        Out     1.017      44.583 r     -         
shift_reg_249_RNIC7TB261_0[51]                  Net          -        -       -          -            1         
u2.u1.shift_reg_296_i_i_a2_0_RNIIICACJ2[53]     ORCALUT4     A        In      0.000      44.583 r     -         
u2.u1.shift_reg_296_i_i_a2_0_RNIIICACJ2[53]     ORCALUT4     Z        Out     1.249      45.832 r     -         
CO2_41                                          Net          -        -       -          -            7         
u2.u1.shift_reg_324_i_i_a2_RNINHT34C1[57]       ORCALUT4     B        In      0.000      45.832 r     -         
u2.u1.shift_reg_324_i_i_a2_RNINHT34C1[57]       ORCALUT4     Z        Out     1.017      46.849 r     -         
shift_reg_324_i_i_a2_RNINHT34C1[57]             Net          -        -       -          -            1         
u2.u1.shift_reg_299_RNI3MG40C3[58]              ORCALUT4     C        In      0.000      46.849 r     -         
u2.u1.shift_reg_299_RNI3MG40C3[58]              ORCALUT4     Z        Out     1.289      48.137 r     -         
CO0_33                                          Net          -        -       -          -            12        
u2.u1.shift_reg_296_RNI3VO18V1[55]              ORCALUT4     A        In      0.000      48.137 r     -         
u2.u1.shift_reg_296_RNI3VO18V1[55]              ORCALUT4     Z        Out     1.017      49.154 r     -         
shift_reg_296_RNI3VO18V1[55]                    Net          -        -       -          -            1         
u2.u1.shift_reg_324_RNI9ROMBB1[58]              ORCALUT4     C        In      0.000      49.154 r     -         
u2.u1.shift_reg_324_RNI9ROMBB1[58]              ORCALUT4     Z        Out     1.265      50.419 r     -         
CO0_25                                          Net          -        -       -          -            8         
u2.u1.shift_reg_374[58]                         ORCALUT4     B        In      0.000      50.419 r     -         
u2.u1.shift_reg_374[58]                         ORCALUT4     Z        Out     1.233      51.652 r     -         
shift_reg_374[58]                               Net          -        -       -          -            6         
u2.u1.shift_reg_374_i_i_a2_RNIDF71AS2_2[57]     ORCALUT4     D        In      0.000      51.652 r     -         
u2.u1.shift_reg_374_i_i_a2_RNIDF71AS2_2[57]     ORCALUT4     Z        Out     1.297      52.949 r     -         
CO0_20                                          Net          -        -       -          -            13        
u2.u1.shift_reg_405_RNI3F6JKS2[63]              ORCALUT4     B        In      0.000      52.949 r     -         
u2.u1.shift_reg_405_RNI3F6JKS2[63]              ORCALUT4     Z        Out     1.301      54.249 r     -         
un1_shift_reg_axb0_1                            Net          -        -       -          -            14        
u2.u1.shift_reg_433_RNIRUVH623_1[62]            ORCALUT4     C        In      0.000      54.249 r     -         
u2.u1.shift_reg_433_RNIRUVH623_1[62]            ORCALUT4     Z        Out     1.017      55.266 r     -         
shift_reg_433_RNIRUVH623_1[62]                  Net          -        -       -          -            1         
u2.u1.shift_reg_405_RNII8I21Q[62]               ORCALUT4     B        In      0.000      55.266 r     -         
u2.u1.shift_reg_405_RNII8I21Q[62]               ORCALUT4     Z        Out     1.225      56.491 r     -         
un1_shift_reg_axb0                              Net          -        -       -          -            5         
u2.u1._l31\.un1_shift_reg_ac0_5                 ORCALUT4     C        In      0.000      56.491 r     -         
u2.u1._l31\.un1_shift_reg_ac0_5                 ORCALUT4     Z        Out     1.193      57.684 f     -         
bcd_code_1_0[29]                                Net          -        -       -          -            4         
u2.u1.bcd_code[31]                              ORCALUT4     C        In      0.000      57.684 f     -         
u2.u1.bcd_code[31]                              ORCALUT4     Z        Out     1.273      58.957 r     -         
lux_data[31]                                    Net          -        -       -          -            9         
u3.data_12_1_am_N_3L3_0_x0                      ORCALUT4     B        In      0.000      58.957 r     -         
u3.data_12_1_am_N_3L3_0_x0                      ORCALUT4     Z        Out     1.017      59.973 f     -         
data_12_1_am_N_3L3_0_x0                         Net          -        -       -          -            1         
u3.data_12_1_am_N_3L3_0                         PFUMX        BLUT     In      0.000      59.973 f     -         
u3.data_12_1_am_N_3L3_0                         PFUMX        Z        Out     0.214      60.188 f     -         
data_12_1_am_N_3L3_0                            Net          -        -       -          -            1         
u3.data_12_1_am[8]                              ORCALUT4     B        In      0.000      60.188 f     -         
u3.data_12_1_am[8]                              ORCALUT4     Z        Out     1.017      61.204 r     -         
data_12_1_am[8]                                 Net          -        -       -          -            1         
u3.data_12_1[8]                                 PFUMX        BLUT     In      0.000      61.204 r     -         
u3.data_12_1[8]                                 PFUMX        Z        Out     -0.033     61.171 r     -         
N_523                                           Net          -        -       -          -            1         
u3.data_12_3[8]                                 L6MUX21      D1       In      0.000      61.171 r     -         
u3.data_12_3[8]                                 L6MUX21      Z        Out     0.265      61.436 r     -         
N_537                                           Net          -        -       -          -            1         
u3.data_12_7_1[8]                               ORCALUT4     A        In      0.000      61.436 r     -         
u3.data_12_7_1[8]                               ORCALUT4     Z        Out     1.017      62.453 f     -         
data_12_7_1[8]                                  Net          -        -       -          -            1         
u3.data_12_7[8]                                 ORCALUT4     D        In      0.000      62.453 f     -         
u3.data_12_7[8]                                 ORCALUT4     Z        Out     0.617      63.070 r     -         
data_12[8]                                      Net          -        -       -          -            1         
u3.data[8]                                      FD1P3AX      D        In      0.000      63.070 r     -         
================================================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      63.070
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -57.981

    Number of logic level(s):                63
    Starting point:                          u1.ch1_dat[7] / Q
    Ending point:                            u3.data[8] / D
    The start point is clocked by            rpr0521rs_driver|clk_400khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                                               Pin      Pin                Arrival      No. of    
Name                                            Type         Name     Dir     Delay      Time         Fan Out(s)
----------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]                                   FD1P3AX      Q        Out     1.256      1.256 r      -         
ch1_dat[7]                                      Net          -        -       -          -            14        
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        A1       In      0.000      1.256 r      -         
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        COUT     Out     1.544      2.800 r      -         
un1_ch1_dat_1_cry_7                             Net          -        -       -          -            1         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        CIN      In      0.000      2.800 r      -         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        S0       Out     1.685      4.485 r      -         
un1_ch1_dat_1[8]                                Net          -        -       -          -            3         
u2.un1_lux_1_d1_39                              ORCALUT4     B        In      0.000      4.485 r      -         
u2.un1_lux_1_d1_39                              ORCALUT4     Z        Out     1.017      5.502 r      -         
un1_lux_1_d1_39                                 Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        C1       In      0.000      5.502 r      -         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        COUT     Out     1.544      7.047 r      -         
un1_lux_1_s0_m1_0_cry_8                         Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        CIN      In      0.000      7.047 r      -         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        COUT     Out     0.143      7.189 r      -         
un1_lux_1_s0_m1_0_cry_10                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        CIN      In      0.000      7.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        COUT     Out     0.143      7.332 r      -         
un1_lux_1_s0_m1_0_cry_12                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        CIN      In      0.000      7.332 r      -         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        COUT     Out     0.143      7.475 r      -         
un1_lux_1_s0_m1_0_cry_14                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        CIN      In      0.000      7.475 r      -         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        COUT     Out     0.143      7.618 r      -         
un1_lux_1_s0_m1_0_cry_16                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        CIN      In      0.000      7.618 r      -         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        COUT     Out     0.143      7.761 r      -         
un1_lux_1_s0_m1_0_cry_18                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        CIN      In      0.000      7.761 r      -         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        COUT     Out     0.143      7.903 r      -         
un1_lux_1_s0_m1_0_cry_20                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        CIN      In      0.000      7.903 r      -         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        COUT     Out     0.143      8.046 r      -         
un1_lux_1_s0_m1_0_cry_22                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        CIN      In      0.000      8.046 r      -         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        COUT     Out     0.143      8.189 r      -         
un1_lux_1_s0_m1_0_cry_24                        Net          -        -       -          -            1         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        CIN      In      0.000      8.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        S0       Out     1.621      9.810 r      -         
un1_lux_1_s0_m1_0_cry_25_0_S0                   Net          -        -       -          -            2         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     A        In      0.000      9.810 r      -         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     Z        Out     1.193      11.003 r     -         
un1_lux_1_s0_m1[27]                             Net          -        -       -          -            4         
u2.u1.shift_reg_34_a0_sx_RNO[34]                ORCALUT4     B        In      0.000      11.003 r     -         
u2.u1.shift_reg_34_a0_sx_RNO[34]                ORCALUT4     Z        Out     1.017      12.020 r     -         
un1_lux_1_s0_rn_0[27]                           Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_sx[34]                    ORCALUT4     B        In      0.000      12.020 r     -         
u2.u1.shift_reg_34_a0_sx[34]                    ORCALUT4     Z        Out     1.017      13.036 r     -         
shift_reg_34_a0_sx[34]                          Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_x1[34]                    ORCALUT4     A        In      0.000      13.036 r     -         
u2.u1.shift_reg_34_a0_x1[34]                    ORCALUT4     Z        Out     1.017      14.053 f     -         
shift_reg_34_a0_x1[34]                          Net          -        -       -          -            1         
u2.u1.shift_reg_34_a0_x1_RNI2H2E7[34]           ORCALUT4     A        In      0.000      14.053 f     -         
u2.u1.shift_reg_34_a0_x1_RNI2H2E7[34]           ORCALUT4     Z        Out     1.193      15.246 f     -         
shift_reg_34_a0_x1_RNI2H2E7[34]                 Net          -        -       -          -            4         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     A        In      0.000      15.246 f     -         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     Z        Out     1.265      16.511 r     -         
CO0_118                                         Net          -        -       -          -            8         
u2.u1.shift_reg_41[33]                          ORCALUT4     B        In      0.000      16.511 r     -         
u2.u1.shift_reg_41[33]                          ORCALUT4     Z        Out     1.289      17.800 r     -         
shift_reg_41[33]                                Net          -        -       -          -            12        
u2.u1.shift_reg_64_i_i_a2_N_3L3                 ORCALUT4     B        In      0.000      17.800 r     -         
u2.u1.shift_reg_64_i_i_a2_N_3L3                 ORCALUT4     Z        Out     1.017      18.816 r     -         
shift_reg_64_i_i_a2_N_3L3                       Net          -        -       -          -            1         
u2.u1.shift_reg_64_i_i_a2_N_4L5                 ORCALUT4     D        In      0.000      18.816 r     -         
u2.u1.shift_reg_64_i_i_a2_N_4L5                 ORCALUT4     Z        Out     1.017      19.833 r     -         
shift_reg_64_i_i_a2_N_4L5                       Net          -        -       -          -            1         
u2.u1.shift_reg_64_i_i_a2[37]                   ORCALUT4     D        In      0.000      19.833 r     -         
u2.u1.shift_reg_64_i_i_a2[37]                   ORCALUT4     Z        Out     1.233      21.066 r     -         
ANB1_112                                        Net          -        -       -          -            6         
u2.u1.shift_reg_74[39]                          ORCALUT4     A        In      0.000      21.066 r     -         
u2.u1.shift_reg_74[39]                          ORCALUT4     Z        Out     1.249      22.315 r     -         
shift_reg_74[39]                                Net          -        -       -          -            7         
u2.u1.shift_reg_87_N_2L1                        ORCALUT4     B        In      0.000      22.315 r     -         
u2.u1.shift_reg_87_N_2L1                        ORCALUT4     Z        Out     1.017      23.332 r     -         
shift_reg_87_N_2L1                              Net          -        -       -          -            1         
u2.u1.shift_reg_87[38]                          ORCALUT4     C        In      0.000      23.332 r     -         
u2.u1.shift_reg_87[38]                          ORCALUT4     Z        Out     1.193      24.524 r     -         
shift_reg_87[38]                                Net          -        -       -          -            4         
u2.u1.shift_reg_87_0_a2_0_a2_RNI2T0CV[37]       ORCALUT4     C        In      0.000      24.524 r     -         
u2.u1.shift_reg_87_0_a2_0_a2_RNI2T0CV[37]       ORCALUT4     Z        Out     1.225      25.749 r     -         
CO0_101                                         Net          -        -       -          -            5         
u2.u1.shift_reg_116_mb_1[42]                    ORCALUT4     B        In      0.000      25.749 r     -         
u2.u1.shift_reg_116_mb_1[42]                    ORCALUT4     Z        Out     1.017      26.766 f     -         
shift_reg_116_mb_1[42]                          Net          -        -       -          -            1         
u2.u1.shift_reg_116_mb[42]                      ORCALUT4     C        In      0.000      26.766 f     -         
u2.u1.shift_reg_116_mb[42]                      ORCALUT4     Z        Out     1.233      27.999 r     -         
shift_reg_116[42]                               Net          -        -       -          -            6         
u2.u1.shift_reg_116_RNI3BOOH1[43]               ORCALUT4     C        In      0.000      27.999 r     -         
u2.u1.shift_reg_116_RNI3BOOH1[43]               ORCALUT4     Z        Out     1.017      29.016 r     -         
SUM1_75_3_N_4L6_N_2L1_sx                        Net          -        -       -          -            1         
u2.u1.shift_reg_116_RNID6ROO2[43]               ORCALUT4     B        In      0.000      29.016 r     -         
u2.u1.shift_reg_116_RNID6ROO2[43]               ORCALUT4     Z        Out     1.017      30.032 f     -         
shift_reg_116_RNID6ROO2[43]                     Net          -        -       -          -            1         
u2.u1.shift_reg_116_i_0_RNIIMJ2Q5[41]           ORCALUT4     D        In      0.000      30.032 f     -         
u2.u1.shift_reg_116_i_0_RNIIMJ2Q5[41]           ORCALUT4     Z        Out     1.017      31.049 r     -         
shift_reg_116_i_0_RNIIMJ2Q5[41]                 Net          -        -       -          -            1         
u2.u1.shift_reg_132_RNIAJNCLO2[43]              ORCALUT4     C        In      0.000      31.049 r     -         
u2.u1.shift_reg_132_RNIAJNCLO2[43]              ORCALUT4     Z        Out     1.017      32.066 r     -         
shift_reg_132_RNIAJNCLO2[43]                    Net          -        -       -          -            1         
u2.u1.shift_reg_151_RNI345SMO2[46]              ORCALUT4     A        In      0.000      32.066 r     -         
u2.u1.shift_reg_151_RNI345SMO2[46]              ORCALUT4     Z        Out     1.225      33.291 r     -         
CO0_82                                          Net          -        -       -          -            5         
u2.u1.shift_reg_167[46]                         PFUMX        C0       In      0.000      33.291 r     -         
u2.u1.shift_reg_167[46]                         PFUMX        Z        Out     1.089      34.380 r     -         
shift_reg_167[46]                               Net          -        -       -          -            4         
u2.u1.shift_reg_167_i_0_RNI13OQV[45]            ORCALUT4     C        In      0.000      34.380 r     -         
u2.u1.shift_reg_167_i_0_RNI13OQV[45]            ORCALUT4     Z        Out     1.277      35.657 r     -         
CO0_76                                          Net          -        -       -          -            10        
u2.u1.shift_reg_189_RNIIGG2B1_3[51]             ORCALUT4     B        In      0.000      35.657 r     -         
u2.u1.shift_reg_189_RNIIGG2B1_3[51]             ORCALUT4     Z        Out     1.225      36.881 r     -         
CO0_72                                          Net          -        -       -          -            5         
u2.u1.shift_reg_227_i_i_a2_0[49]                ORCALUT4     B        In      0.000      36.881 r     -         
u2.u1.shift_reg_227_i_i_a2_0[49]                ORCALUT4     Z        Out     1.249      38.130 r     -         
shift_reg_227_i_i_a2_0[49]                      Net          -        -       -          -            7         
u2.u1.shift_reg_249_N_2L1_0                     ORCALUT4     D        In      0.000      38.130 r     -         
u2.u1.shift_reg_249_N_2L1_0                     ORCALUT4     Z        Out     1.017      39.147 r     -         
shift_reg_249_N_2L1_0                           Net          -        -       -          -            1         
u2.u1.shift_reg_249[51]                         ORCALUT4     D        In      0.000      39.147 r     -         
u2.u1.shift_reg_249[51]                         ORCALUT4     Z        Out     1.233      40.380 r     -         
shift_reg_249[51]                               Net          -        -       -          -            6         
u2.u1.shift_reg_271_1[50]                       ORCALUT4     C        In      0.000      40.380 r     -         
u2.u1.shift_reg_271_1[50]                       ORCALUT4     Z        Out     1.153      41.533 r     -         
shift_reg_271_1[50]                             Net          -        -       -          -            3         
u2.u1.shift_reg_271_1_RNI2LOLQL_0[50]           ORCALUT4     D        In      0.000      41.533 r     -         
u2.u1.shift_reg_271_1_RNI2LOLQL_0[50]           ORCALUT4     Z        Out     1.017      42.549 r     -         
CO2_45_N_3L4_sx                                 Net          -        -       -          -            1         
u2.u1.shift_reg_271_i_i_a2_RNIABEM3N_0[49]      ORCALUT4     B        In      0.000      42.549 r     -         
u2.u1.shift_reg_271_i_i_a2_RNIABEM3N_0[49]      ORCALUT4     Z        Out     1.017      43.566 f     -         
shift_reg_271_i_i_a2_RNIABEM3N_0[49]            Net          -        -       -          -            1         
u2.u1.shift_reg_249_RNIC7TB261_0[51]            ORCALUT4     B        In      0.000      43.566 f     -         
u2.u1.shift_reg_249_RNIC7TB261_0[51]            ORCALUT4     Z        Out     1.017      44.583 r     -         
shift_reg_249_RNIC7TB261_0[51]                  Net          -        -       -          -            1         
u2.u1.shift_reg_296_i_i_a2_0_RNIIICACJ2[53]     ORCALUT4     A        In      0.000      44.583 r     -         
u2.u1.shift_reg_296_i_i_a2_0_RNIIICACJ2[53]     ORCALUT4     Z        Out     1.249      45.832 r     -         
CO2_41                                          Net          -        -       -          -            7         
u2.u1.shift_reg_324_i_i_a2_RNINHT34C1[57]       ORCALUT4     B        In      0.000      45.832 r     -         
u2.u1.shift_reg_324_i_i_a2_RNINHT34C1[57]       ORCALUT4     Z        Out     1.017      46.849 r     -         
shift_reg_324_i_i_a2_RNINHT34C1[57]             Net          -        -       -          -            1         
u2.u1.shift_reg_299_RNI3MG40C3[58]              ORCALUT4     C        In      0.000      46.849 r     -         
u2.u1.shift_reg_299_RNI3MG40C3[58]              ORCALUT4     Z        Out     1.289      48.137 r     -         
CO0_33                                          Net          -        -       -          -            12        
u2.u1.shift_reg_296_RNI3VO18V1[55]              ORCALUT4     A        In      0.000      48.137 r     -         
u2.u1.shift_reg_296_RNI3VO18V1[55]              ORCALUT4     Z        Out     1.017      49.154 r     -         
shift_reg_296_RNI3VO18V1[55]                    Net          -        -       -          -            1         
u2.u1.shift_reg_324_RNI9ROMBB1[58]              ORCALUT4     C        In      0.000      49.154 r     -         
u2.u1.shift_reg_324_RNI9ROMBB1[58]              ORCALUT4     Z        Out     1.265      50.419 r     -         
CO0_25                                          Net          -        -       -          -            8         
u2.u1.shift_reg_374[58]                         ORCALUT4     B        In      0.000      50.419 r     -         
u2.u1.shift_reg_374[58]                         ORCALUT4     Z        Out     1.233      51.652 r     -         
shift_reg_374[58]                               Net          -        -       -          -            6         
u2.u1.shift_reg_374_i_i_a2_RNIDF71AS2_2[57]     ORCALUT4     D        In      0.000      51.652 r     -         
u2.u1.shift_reg_374_i_i_a2_RNIDF71AS2_2[57]     ORCALUT4     Z        Out     1.297      52.949 r     -         
CO0_20                                          Net          -        -       -          -            13        
u2.u1.shift_reg_405_RNI3F6JKS2[63]              ORCALUT4     B        In      0.000      52.949 r     -         
u2.u1.shift_reg_405_RNI3F6JKS2[63]              ORCALUT4     Z        Out     1.301      54.249 r     -         
un1_shift_reg_axb0_1                            Net          -        -       -          -            14        
u2.u1.shift_reg_433_RNIRUVH623_1[62]            ORCALUT4     C        In      0.000      54.249 r     -         
u2.u1.shift_reg_433_RNIRUVH623_1[62]            ORCALUT4     Z        Out     1.017      55.266 r     -         
shift_reg_433_RNIRUVH623_1[62]                  Net          -        -       -          -            1         
u2.u1.shift_reg_405_RNII8I21Q[62]               ORCALUT4     B        In      0.000      55.266 r     -         
u2.u1.shift_reg_405_RNII8I21Q[62]               ORCALUT4     Z        Out     1.225      56.491 r     -         
un1_shift_reg_axb0                              Net          -        -       -          -            5         
u2.u1._l31\.un1_shift_reg_ac0_5                 ORCALUT4     C        In      0.000      56.491 r     -         
u2.u1._l31\.un1_shift_reg_ac0_5                 ORCALUT4     Z        Out     1.193      57.684 f     -         
bcd_code_1_0[29]                                Net          -        -       -          -            4         
u2.u1.bcd_code[31]                              ORCALUT4     C        In      0.000      57.684 f     -         
u2.u1.bcd_code[31]                              ORCALUT4     Z        Out     1.273      58.957 r     -         
lux_data[31]                                    Net          -        -       -          -            9         
u3.data_12_1_am_N_3L3_0_x0                      ORCALUT4     B        In      0.000      58.957 r     -         
u3.data_12_1_am_N_3L3_0_x0                      ORCALUT4     Z        Out     1.017      59.973 f     -         
data_12_1_am_N_3L3_0_x0                         Net          -        -       -          -            1         
u3.data_12_1_am_N_3L3_0                         PFUMX        BLUT     In      0.000      59.973 f     -         
u3.data_12_1_am_N_3L3_0                         PFUMX        Z        Out     0.214      60.188 f     -         
data_12_1_am_N_3L3_0                            Net          -        -       -          -            1         
u3.data_12_1_am[8]                              ORCALUT4     B        In      0.000      60.188 f     -         
u3.data_12_1_am[8]                              ORCALUT4     Z        Out     1.017      61.204 r     -         
data_12_1_am[8]                                 Net          -        -       -          -            1         
u3.data_12_1[8]                                 PFUMX        BLUT     In      0.000      61.204 r     -         
u3.data_12_1[8]                                 PFUMX        Z        Out     -0.033     61.171 r     -         
N_523                                           Net          -        -       -          -            1         
u3.data_12_3[8]                                 L6MUX21      D1       In      0.000      61.171 r     -         
u3.data_12_3[8]                                 L6MUX21      Z        Out     0.265      61.436 r     -         
N_537                                           Net          -        -       -          -            1         
u3.data_12_7_1[8]                               ORCALUT4     A        In      0.000      61.436 r     -         
u3.data_12_7_1[8]                               ORCALUT4     Z        Out     1.017      62.453 f     -         
data_12_7_1[8]                                  Net          -        -       -          -            1         
u3.data_12_7[8]                                 ORCALUT4     D        In      0.000      62.453 f     -         
u3.data_12_7[8]                                 ORCALUT4     Z        Out     0.617      63.070 r     -         
data_12[8]                                      Net          -        -       -          -            1         
u3.data[8]                                      FD1P3AX      D        In      0.000      63.070 r     -         
================================================================================================================




====================================
<a name=clockReport36></a>Detailed Report for Clock: rpr0521rs_driver|dat_valid_derived_clock</a>
====================================



<a name=startingSlack37></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                                                          Arrival          
Instance            Reference                                    Type        Pin     Net              Time        Slack
                    Clock                                                                                              
-----------------------------------------------------------------------------------------------------------------------
u2.prox_dat0[0]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[0]     1.044       2.365
u2.prox_dat1[0]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[0]     0.972       2.437
u2.prox_dat0[1]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[1]     1.044       2.507
u2.prox_dat0[2]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[2]     1.044       2.507
u2.prox_dat1[1]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[1]     0.972       2.579
u2.prox_dat1[2]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[2]     0.972       2.579
u2.prox_dat0[3]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[3]     1.044       2.650
u2.prox_dat0[4]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[4]     1.044       2.650
u2.prox_dat1[3]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[3]     0.972       2.722
u2.prox_dat1[4]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[4]     0.972       2.722
=======================================================================================================================


<a name=endingSlack38></a>Ending Points with Worst Slack</a>
******************************

                     Starting                                                                                  Required          
Instance             Reference                                    Type        Pin     Net                      Time         Slack
                     Clock                                                                                                       
---------------------------------------------------------------------------------------------------------------------------------
u2.prox_dat2[9]      rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     SP      un1_prox_dat0_2lto15     9.528        2.365
u2.prox_dat2[10]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     SP      un1_prox_dat0_2lto15     9.528        2.365
u2.prox_dat2[11]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     SP      un1_prox_dat0_2lto15     9.528        2.365
buzz_ctrl            rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       buzz_ctrl4               5.089        3.252
u2.prox_dat1[9]      rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[9]             9.894        8.787
u2.prox_dat1[10]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[10]            9.894        8.787
u2.prox_dat1[11]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[11]            9.894        8.787
u2.prox_dat2[9]      rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     D       prox_dat0[9]             9.894        8.787
u2.prox_dat2[10]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     D       prox_dat0[10]            9.894        8.787
u2.prox_dat2[11]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     D       prox_dat0[11]            9.894        8.787
=================================================================================================================================



<a name=worstPaths39></a>Worst Path Information</a>
<a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srr:srsfC:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srs:fp:221666:224834:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.365

    Number of logic level(s):                10
    Starting point:                          u2.prox_dat0[0] / Q
    Ending point:                            u2.prox_dat2[9] / SP
    The start point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:rpr0521rs_driver|dat_valid_derived_clock to c:rpr0521rs_driver|dat_valid_derived_clock)

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u2.prox_dat0[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
prox_dat0[0]                    Net          -        -       -         -           2         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        B1       In      0.000     1.044 r     -         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un1_prox_dat0_1_cry_0           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un1_prox_dat0_1_cry_2           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un1_prox_dat0_1_cry_4           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un1_prox_dat0_1_cry_6           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un1_prox_dat0_1_cry_8           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un1_prox_dat0_1_cry_10          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        COUT     Out     0.143     3.445 r     -         
un1_prox_dat0_1_cry_12          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        CIN      In      0.000     3.445 r     -         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        S1       Out     1.549     4.994 r     -         
un1_prox_dat0_1[14]             Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     B        In      0.000     4.994 r     -         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     Z        Out     1.017     6.011 f     -         
un1_prox_dat0_2lto15_1          Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15         ORCALUT4     D        In      0.000     6.011 f     -         
u2.un1_prox_dat0_2lto15         ORCALUT4     Z        Out     1.153     7.164 f     -         
un1_prox_dat0_2lto15            Net          -        -       -         -           3         
u2.prox_dat2[9]                 FD1P3AX      SP       In      0.000     7.164 f     -         
==============================================================================================


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.365

    Number of logic level(s):                10
    Starting point:                          u2.prox_dat0[0] / Q
    Ending point:                            u2.prox_dat2[9] / SP
    The start point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:rpr0521rs_driver|dat_valid_derived_clock to c:rpr0521rs_driver|dat_valid_derived_clock)

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u2.prox_dat0[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
prox_dat0[0]                    Net          -        -       -         -           2         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        B1       In      0.000     1.044 r     -         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un1_prox_dat0_1_cry_0           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un1_prox_dat0_1_cry_2           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un1_prox_dat0_1_cry_4           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un1_prox_dat0_1_cry_6           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un1_prox_dat0_1_cry_8           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un1_prox_dat0_1_cry_10          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        COUT     Out     0.143     3.445 r     -         
un1_prox_dat0_1_cry_12          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        CIN      In      0.000     3.445 r     -         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        S0       Out     1.549     4.994 r     -         
un1_prox_dat0_1[13]             Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     A        In      0.000     4.994 r     -         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     Z        Out     1.017     6.011 f     -         
un1_prox_dat0_2lto15_1          Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15         ORCALUT4     D        In      0.000     6.011 f     -         
u2.un1_prox_dat0_2lto15         ORCALUT4     Z        Out     1.153     7.164 f     -         
un1_prox_dat0_2lto15            Net          -        -       -         -           3         
u2.prox_dat2[9]                 FD1P3AX      SP       In      0.000     7.164 f     -         
==============================================================================================


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.365

    Number of logic level(s):                10
    Starting point:                          u2.prox_dat0[0] / Q
    Ending point:                            u2.prox_dat2[11] / SP
    The start point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:rpr0521rs_driver|dat_valid_derived_clock to c:rpr0521rs_driver|dat_valid_derived_clock)

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u2.prox_dat0[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
prox_dat0[0]                    Net          -        -       -         -           2         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        B1       In      0.000     1.044 r     -         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un1_prox_dat0_1_cry_0           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un1_prox_dat0_1_cry_2           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un1_prox_dat0_1_cry_4           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un1_prox_dat0_1_cry_6           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un1_prox_dat0_1_cry_8           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un1_prox_dat0_1_cry_10          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        COUT     Out     0.143     3.445 r     -         
un1_prox_dat0_1_cry_12          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        CIN      In      0.000     3.445 r     -         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        S1       Out     1.549     4.994 r     -         
un1_prox_dat0_1[14]             Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     B        In      0.000     4.994 r     -         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     Z        Out     1.017     6.011 f     -         
un1_prox_dat0_2lto15_1          Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15         ORCALUT4     D        In      0.000     6.011 f     -         
u2.un1_prox_dat0_2lto15         ORCALUT4     Z        Out     1.153     7.164 f     -         
un1_prox_dat0_2lto15            Net          -        -       -         -           3         
u2.prox_dat2[11]                FD1P3AX      SP       In      0.000     7.164 f     -         
==============================================================================================




====================================
<a name=clockReport40></a>Detailed Report for Clock: segment_scan|clk_40khz_derived_clock</a>
====================================



<a name=startingSlack41></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                                                      Arrival          
Instance            Reference                                Type        Pin     Net              Time        Slack
                    Clock                                                                                          
-------------------------------------------------------------------------------------------------------------------
u3.cnt_main[2]      segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       cnt_main[2]      1.352       2.805
u3.cnt_write[1]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[1]     1.232       2.810
u3.cnt_write[2]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[2]     1.188       2.854
u3.cnt_write[4]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[4]     1.148       2.894
u3.cnt_write[3]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[3]     1.108       2.934
u3.state[1]         segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       state[1]         1.252       4.015
u3.cnt_write[0]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[0]     1.204       4.063
u3.cnt_write[5]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[5]     1.204       4.063
u3.cnt_main[1]      segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       cnt_main[1]      1.314       4.717
u3.state[0]         segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       state[0]         1.236       6.980
===================================================================================================================


<a name=endingSlack42></a>Ending Points with Worst Slack</a>
******************************

                    Starting                                                                        Required          
Instance            Reference                                Type        Pin     Net                Time         Slack
                    Clock                                                                                             
----------------------------------------------------------------------------------------------------------------------
u3.data[8]          segment_scan|clk_40khz_derived_clock     FD1P3AX     D       data_12[8]         10.089       2.805
u3.cnt_write[5]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[5]     9.894        2.810
u3.cnt_write[3]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[3]     9.894        2.953
u3.cnt_write[4]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[4]     9.894        2.953
u3.cnt_write[1]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[1]     9.894        3.095
u3.cnt_write[2]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[2]     9.894        3.095
u3.data[13]         segment_scan|clk_40khz_derived_clock     FD1P3AX     D       data_12[13]        10.089       4.680
u3.cnt_write[0]     segment_scan|clk_40khz_derived_clock     FD1P3AX     SP      N_119_i            9.528        4.822
u3.cnt_write[1]     segment_scan|clk_40khz_derived_clock     FD1P3AX     SP      N_119_i            9.528        4.822
u3.cnt_write[2]     segment_scan|clk_40khz_derived_clock     FD1P3AX     SP      N_119_i            9.528        4.822
======================================================================================================================



<a name=worstPaths43></a>Worst Path Information</a>
<a href="C:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srr:srsfC:\Users\lumfl\Downloads\NetDisk\V4.0\STEP-MXO2\myTrafficLight\impl1\prox_detect_impl1.srs:fp:239383:241975:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         10.089

    - Propagation time:                      7.284
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.805

    Number of logic level(s):                8
    Starting point:                          u3.cnt_main[2] / Q
    Ending point:                            u3.data[8] / D
    The start point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:segment_scan|clk_40khz_derived_clock to c:segment_scan|clk_40khz_derived_clock)

Instance / Net                              Pin      Pin                Arrival     No. of    
Name                           Type         Name     Dir     Delay      Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u3.cnt_main[2]                 FD1S3AX      Q        Out     1.352      1.352 r     -         
cnt_main[2]                    Net          -        -       -          -           49        
u3.data_12_1_amcf1_N_5L8_1     ORCALUT4     C        In      0.000      1.352 r     -         
u3.data_12_1_amcf1_N_5L8_1     ORCALUT4     Z        Out     1.017      2.369 r     -         
data_12_1_amcf1_N_5L8_1        Net          -        -       -          -           1         
u3.data_12_1_amcf1_N_5L8       ORCALUT4     D        In      0.000      2.369 r     -         
u3.data_12_1_amcf1_N_5L8       ORCALUT4     Z        Out     1.017      3.385 r     -         
data_12_1_amcf1_N_5L8          Net          -        -       -          -           1         
u3.data_12_1_amcf1[8]          ORCALUT4     D        In      0.000      3.385 r     -         
u3.data_12_1_amcf1[8]          ORCALUT4     Z        Out     1.017      4.402 r     -         
data_12_1_amcf1[8]             Net          -        -       -          -           1         
u3.data_12_1_am[8]             ORCALUT4     C        In      0.000      4.402 r     -         
u3.data_12_1_am[8]             ORCALUT4     Z        Out     1.017      5.419 r     -         
data_12_1_am[8]                Net          -        -       -          -           1         
u3.data_12_1[8]                PFUMX        BLUT     In      0.000      5.419 r     -         
u3.data_12_1[8]                PFUMX        Z        Out     -0.033     5.386 r     -         
N_523                          Net          -        -       -          -           1         
u3.data_12_3[8]                L6MUX21      D1       In      0.000      5.386 r     -         
u3.data_12_3[8]                L6MUX21      Z        Out     0.265      5.651 r     -         
N_537                          Net          -        -       -          -           1         
u3.data_12_7_1[8]              ORCALUT4     A        In      0.000      5.651 r     -         
u3.data_12_7_1[8]              ORCALUT4     Z        Out     1.017      6.667 f     -         
data_12_7_1[8]                 Net          -        -       -          -           1         
u3.data_12_7[8]                ORCALUT4     D        In      0.000      6.667 f     -         
u3.data_12_7[8]                ORCALUT4     Z        Out     0.617      7.284 r     -         
data_12[8]                     Net          -        -       -          -           1         
u3.data[8]                     FD1P3AX      D        In      0.000      7.284 r     -         
==============================================================================================


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      7.085
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.810

    Number of logic level(s):                6
    Starting point:                          u3.cnt_write[1] / Q
    Ending point:                            u3.cnt_write[5] / D
    The start point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:segment_scan|clk_40khz_derived_clock to c:segment_scan|clk_40khz_derived_clock)

Instance / Net                                       Pin      Pin               Arrival     No. of    
Name                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------
u3.cnt_write[1]                         FD1P3AX      Q        Out     1.232     1.232 r     -         
cnt_write[1]                            Net          -        -       -         -           10        
u3.state_ns_0_a2_0_a2_1[0]              ORCALUT4     A        In      0.000     1.232 r     -         
u3.state_ns_0_a2_0_a2_1[0]              ORCALUT4     Z        Out     1.225     2.457 f     -         
N_169                                   Net          -        -       -         -           5         
u3.state_ns_0_a2_0_a2_1_RNIGUQ8P[0]     ORCALUT4     D        In      0.000     2.457 f     -         
u3.state_ns_0_a2_0_a2_1_RNIGUQ8P[0]     ORCALUT4     Z        Out     1.249     3.705 f     -         
cnt_write                               Net          -        -       -         -           7         
u3.cnt_write_cry_0[0]                   CCU2D        A1       In      0.000     3.705 f     -         
u3.cnt_write_cry_0[0]                   CCU2D        COUT     Out     1.544     5.250 r     -         
cnt_write_cry[0]                        Net          -        -       -         -           1         
u3.cnt_write_cry_0[1]                   CCU2D        CIN      In      0.000     5.250 r     -         
u3.cnt_write_cry_0[1]                   CCU2D        COUT     Out     0.143     5.393 r     -         
cnt_write_cry[2]                        Net          -        -       -         -           1         
u3.cnt_write_cry_0[3]                   CCU2D        CIN      In      0.000     5.393 r     -         
u3.cnt_write_cry_0[3]                   CCU2D        COUT     Out     0.143     5.535 r     -         
cnt_write_cry[4]                        Net          -        -       -         -           1         
u3.cnt_write_s_0[5]                     CCU2D        CIN      In      0.000     5.535 r     -         
u3.cnt_write_s_0[5]                     CCU2D        S0       Out     1.549     7.085 r     -         
cnt_write_s[5]                          Net          -        -       -         -           1         
u3.cnt_write[5]                         FD1P3AX      D        In      0.000     7.085 r     -         
======================================================================================================


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      7.085
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.810

    Number of logic level(s):                6
    Starting point:                          u3.cnt_write[1] / Q
    Ending point:                            u3.cnt_write[5] / D
    The start point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:segment_scan|clk_40khz_derived_clock to c:segment_scan|clk_40khz_derived_clock)

Instance / Net                                       Pin      Pin               Arrival     No. of    
Name                                    Type         Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------
u3.cnt_write[1]                         FD1P3AX      Q        Out     1.232     1.232 r     -         
cnt_write[1]                            Net          -        -       -         -           10        
u3.state_ns_0_a2_0_a2_1[0]              ORCALUT4     A        In      0.000     1.232 r     -         
u3.state_ns_0_a2_0_a2_1[0]              ORCALUT4     Z        Out     1.225     2.457 f     -         
N_169                                   Net          -        -       -         -           5         
u3.state_ns_0_a2_0_a2_1_RNIGUQ8P[0]     ORCALUT4     D        In      0.000     2.457 f     -         
u3.state_ns_0_a2_0_a2_1_RNIGUQ8P[0]     ORCALUT4     Z        Out     1.249     3.705 f     -         
cnt_write                               Net          -        -       -         -           7         
u3.cnt_write_cry_0[0]                   CCU2D        B0       In      0.000     3.705 f     -         
u3.cnt_write_cry_0[0]                   CCU2D        COUT     Out     1.544     5.250 r     -         
cnt_write_cry[0]                        Net          -        -       -         -           1         
u3.cnt_write_cry_0[1]                   CCU2D        CIN      In      0.000     5.250 r     -         
u3.cnt_write_cry_0[1]                   CCU2D        COUT     Out     0.143     5.393 r     -         
cnt_write_cry[2]                        Net          -        -       -         -           1         
u3.cnt_write_cry_0[3]                   CCU2D        CIN      In      0.000     5.393 r     -         
u3.cnt_write_cry_0[3]                   CCU2D        COUT     Out     0.143     5.535 r     -         
cnt_write_cry[4]                        Net          -        -       -         -           1         
u3.cnt_write_s_0[5]                     CCU2D        CIN      In      0.000     5.535 r     -         
u3.cnt_write_s_0[5]                     CCU2D        S0       Out     1.549     7.085 r     -         
cnt_write_s[5]                          Net          -        -       -         -           1         
u3.cnt_write[5]                         FD1P3AX      D        In      0.000     7.085 r     -         
======================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:03m:26s; CPU Time elapsed 0h:03m:26s; Memory used current: 367MB peak: 593MB)


Finished timing report (Real Time elapsed 0h:03m:26s; CPU Time elapsed 0h:03m:26s; Memory used current: 367MB peak: 593MB)

---------------------------------------
<a name=resourceUsage44></a>Resource Usage Report</a>
Part: lcmxo2_4000hc-5

Register bits: 634 of 4320 (15%)
PIC Latch:       0
I/O cells:       34


Details:
BB:             1
CCU2D:          534
FD1P3AX:        464
FD1P3AY:        3
FD1S3AX:        160
FD1S3AY:        1
GSR:            1
IB:             2
IFS1P3DX:       1
INV:            19
L6MUX21:        15
OB:             22
OBZ:            9
OFS1P3BX:       1
OFS1P3DX:       3
OFS1P3IX:       1
ORCALUT4:       1565
PFUMX:          91
PUR:            1
VHI:            9
VLO:            9
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:03m:27s; CPU Time elapsed 0h:03m:26s; Memory used current: 147MB peak: 593MB)

Process took 0h:03m:27s realtime, 0h:03m:26s cputime
# Fri Mar  7 12:49:46 2025

###########################################################]

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